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* i915g: add pineview pci idsDaniel Vetter2010-11-212-0/+10
| | | | | | Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: s/hw_tiled/tilingDaniel Vetter2010-11-212-6/+7
| | | | | | | | | | More in line with other intel drivers. Change to use enum by Jakob Bornecrantz. Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: rip out ->sw_tiledDaniel Vetter2010-11-214-15/+0
| | | | | | | | | | | | | | | | | | It looks like this was meant to facilitate unfenced access to textures/ color/renderbuffers. It's totally incomplete and fundamentally broken on a few levels: - broken: The kernel needs to about every tiled bo to fix up bit17 swizzling on swap-in. - unflexible: fenced/unfenced relocs from execbuffer2 do the same, much simpler. - unneeded: with relaxed fencing tiled gem bos are as memory-efficient as this trick. Hence kill it. Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* r300g: silence guard band cap errorsJoakim Sindholt2010-11-211-0/+7
| | | | | | Somebody should find out what these are. It can be found on Windows getting a D3DCAPS9 from IDirect3D9::GetCaps() and reading the GuardBand* values.
* st/vega: Fix vgReadPixels with a subrectangle.Chia-I Wu2010-11-211-4/+12
| | | | | | | Fix a crash when the subrectangle is not inside the fb. Fix wrong pipe transfer when sx > 0 or sy + height != fb->height. This fixes "readpixels" demo.
* st/vega: Set wrap_r for mask and blend samplers.Chia-I Wu2010-11-211-0/+2
| | | | | | | | | | | These two samplers use non-normalized texture coordinates. wrap_r cannot be PIPE_TEX_WRAP_REPEAT (the default). This fixes sp_tex_sample.c:1790:get_linear_unorm_wrap: Assertion `0' failed assertion failure.
* st/vega: vegaLookupSingle should validate the state.Chia-I Wu2010-11-211-0/+2
| | | | Fix "lookup" demo crash.
* tgsi: Add STENCIL to text parser.Chia-I Wu2010-11-211-1/+2
| | | | | | | | | Fix OpenVG "filter" demo Program received signal SIGSEGV, Segmentation fault. 0xb7153dc9 in str_match_no_case (pcur=0xbfffe564, str=0x0) at tgsi/tgsi_text.c:86 86 while (*str != '\0' && *str == uprcase( *cur )) {
* mesa: Clean up header file inclusion in stencil.h.Vinson Lee2010-11-201-1/+2
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* mesa: Clean up header file inclusion in shared.h.Vinson Lee2010-11-201-1/+1
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* mesa: Clean up header file inclusion in shaderapi.h.Vinson Lee2010-11-201-1/+3
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* mesa: Clean up header file inclusion in scissor.h.Vinson Lee2010-11-201-1/+2
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* mesa: Clean up header file inclusion in renderbuffer.h.Vinson Lee2010-11-201-1/+1
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* mesa: Clean up header file inclusion in readpix.h.Vinson Lee2010-11-201-1/+2
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* mesa: Clean up header file inclusion in rastpos.h.Vinson Lee2010-11-201-1/+4
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* mesa: Clean up header file inclusion in polygon.h.Vinson Lee2010-11-201-1/+2
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* intel: Remove unnecessary header.Vinson Lee2010-11-201-1/+0
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* r600: Remove unnecesary header.Vinson Lee2010-11-201-1/+0
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* swrast: Remove unnecessary header.Vinson Lee2010-11-201-1/+0
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* st/mesa: Remove unnecessary headers.Vinson Lee2010-11-202-2/+0
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* scons: Define IN_DRI_DRIVER.Chia-I Wu2010-11-201-0/+4
| | | | | The define is required for DRI drivers. It is not needed for libgl-xlib, but the overhead it introduces should be minor.
* nvfx: only expose one rt on nv30Xavier Chantry2010-11-201-1/+1
| | | | We do not know how to use more, GL_ARB_draw_buffers is not exposed on blob.
* r600g: Fix location for clip plane registersOwen W. Taylor2010-11-202-8/+8
| | | | | | | | The stride between the different clip plane registers was incorrect. https://bugs.freedesktop.org/show_bug.cgi?id=31788 agd5f: fix evergreen as well.
* r300g: fix rendering with no vertex elementsMarek Olšák2010-11-204-5/+40
| | | | | Fixes glsl-vs-point-size, although I meant to fix glsl-novertexdata. Since swrast fails glsl-novertexdata too, I guess it's a core issue.
* i965: Remove duplicate MRF writes in the FS backend.Eric Anholt2010-11-192-0/+152
| | | | | | | | | | This is quite common for multitexture sampling, and not only cuts down on the second and later set of MOVs, but typically also allows compute-to-MRF on the first set. No statistically siginficant performance difference in nexuiz (n=3), but it reduces instruction count in one of its shaders and seems like a good idea.
* i965: Improve compute-to-mrf.Eric Anholt2010-11-191-53/+49
| | | | | | | | | | | | We were skipping it if the instruction producing the value we were going to compute-to-mrf used its result reg as a source reg. This meant that the typical "write interpolated color to fragment color" or "texture from interpolated texcoord" shader didn't compute-to-MRF. Just don't check for the interference cases until after we've checked if this is the instruction we wanted to compute-to-MRF. Improves nexuiz high-settings performance on my laptop 0.48% +- 0.08% (n=3).
* ir_to_mesa: Detect and emit MOV_SATs for saturate constructs.Eric Anholt2010-11-191-0/+32
| | | | | The goal here is to avoid regressing performance on ir_to_mesa drivers for fixed function fragment shaders requiring saturates.
* i965: Recognize saturates and turn them into a saturated mov.Eric Anholt2010-11-192-0/+27
| | | | | | On pre-gen6, this turns 4 instructions into 1. We could still do better by folding the saturate into the instruction generating the value if nobody else uses it, but that should be a separate pass.
* glsl: Add a helper function for determining if an rvalue could be a saturate.Eric Anholt2010-11-192-0/+58
| | | | | | Hardware pretty commonly has saturate modifiers on instructions, and this can be used in codegen to produce those, without everyone else needing to understand clamping other than min and max.
* i965: Fold constants into the second arg of BRW_SEL as well.Eric Anholt2010-11-191-0/+1
| | | | This hits a common case with min/max operations.
* i965: Remove extra \n at the end of every instruction in INTEL_DEBUG=wm.Eric Anholt2010-11-191-1/+0
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* i965: Just use memset() to clear most members in FS constructors.Eric Anholt2010-11-191-18/+11
| | | | This should make it a lot harder to forget to zero things.
* i965: Fix compute_to_mrf to not move a MRF write up into another live range.Eric Anholt2010-11-191-7/+5
| | | | Fixes glsl-fs-copy-propagation-texcoords-1.
* mesa: Include C++ files in the makedepend of DRI drivers.Eric Anholt2010-11-191-2/+3
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* glsl: Fix type of label 'default' in switch statement.Vinson Lee2010-11-191-1/+1
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* glsl: Add lower_vector.cpp to SConscript.Vinson Lee2010-11-191-0/+1
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* glsl: Fix matrix constructors with vector parametersIan Romanick2010-11-191-9/+9
| | | | | | | When the semantics of write masks in assignments were changed, this code was not correctly updated. Fixes piglit test glsl-mat-from-vec-ctor-01.
* glsl: Combine many instruction lowering passes into one.Kenneth Graunke2010-11-1911-383/+281
| | | | | | | This should save on the overhead of tree-walking and provide a convenient place to add more instruction lowering in the future. Signed-off-by: Ian Romanick <[email protected]>
* glsl: Simplify a type check by using type->is_integer().Kenneth Graunke2010-11-191-2/+1
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* glsl: Add ir_quadop_vector expressionIan Romanick2010-11-1911-6/+460
| | | | | | | | | | The vector operator collects 2, 3, or 4 scalar components into a vector. Doing this has several advantages. First, it will make ud-chain tracking for components of vectors much easier. Second, a later optimization pass could collect scalars into vectors to allow generation of SWZ instructions (or similar as operands to other instructions on R200 and i915). It also enables an easy way to generate IR for SWZ instructions in the ARB_vertex_program assembler.
* glsl: Add unary ir_expression constructorIan Romanick2010-11-192-0/+21
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* glsl: Add ir_rvalue::is_negative_one predicateIan Romanick2010-11-192-3/+58
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* glsl: Eliminate assumptions about size of ir_expression::operandsIan Romanick2010-11-197-7/+13
| | | | This may grow in the near future.
* glsl: Add ir_unop_sin_reduced and ir_unop_cos_reducedIan Romanick2010-11-196-0/+120
| | | | | | | | | | | | The operate just like ir_unop_sin and ir_unop_cos except that they expect their inputs to be limited to the range [-pi, pi]. Several GPUs require this limited range for their sine and cosine instructions, so having these as operations (along with a to-be-written lowering pass) helps this architectures. These new operations also matche the semantics of the GL_ARB_fragment_program SCS instruction. Having these as operations helps in generating GLSL IR directly from assembly fragment programs.
* r600g: use full range of VS resources for vertex samplersAlex Deucher2010-11-193-4/+2
| | | | | Now that we have fetch shaders, the full range of VS resources can be used for sampling.
* r600g: use meaningful defines for chiprevAlex Deucher2010-11-193-19/+24
| | | | Makes the code much clearer.
* r600g: translate ARR instruction for evergreenAlex Deucher2010-11-191-4/+13
| | | | | evergreen variant of: 9f7ec103e26c67cb077fd7d94d2fb68562b86c40
* r600g: add fetch shader capabilitiesJerome Glisse2010-11-1911-12/+125
| | | | | | | | Use fetch shader instead of having fetch instruction in the vertex shader. Allow to restrict shader update to a smaller part when vertex buffer input layout changes. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: All EVENT_WRITE packets need the EVENT_INDEX fieldAlex Deucher2010-11-192-13/+13
| | | | 6xx-evergreen
* dri/nouveau: Clean up magic numbers in get_rt_formatViktor Novotný2010-11-193-13/+13
| | | | | Signed-off-by: Viktor Novotný <[email protected]> Signed-off-by: Francisco Jerez <[email protected]>
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