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* vc4: Keep an array of pointers to instructions defining the temps around.Eric Anholt2015-02-198-68/+67
| | | | | The optimization passes are always regenerating it and throwing it away, but it's not hard to keep track of.
* vc4: Move qir_uniform() and the constant-value versions to vc4_qir.c/h.Eric Anholt2015-02-193-45/+49
| | | | | I may want them in optimization passes, and they're not really particular to the program translation stage.
* vc4: Enforce one-uniform-per-instruction after optimization.Eric Anholt2015-02-196-50/+209
| | | | | | | | | | | | | | | This lets us more intelligently decide which uniform values should be put into temporaries, by choosing the most reused values to push to temps first. total uniforms in shared programs: 13457 -> 13433 (-0.18%) uniforms in affected programs: 1524 -> 1500 (-1.57%) total instructions in shared programs: 40198 -> 40019 (-0.45%) instructions in affected programs: 6027 -> 5848 (-2.97%) I noticed this opportunity because with the NIR work, some programs were happening to make different uniform copy propagation choices that significantly increased instruction counts.
* vc4: Rename add_uniform() to qir_uniform().Eric Anholt2015-02-191-15/+15
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* vc4: Shut up runtime warnings about new pipe caps.Eric Anholt2015-02-191-0/+2
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* i965/vec4: Add and use byte-MOV instruction for unpack 4x8.Matt Turner2015-02-194-2/+21
| | | | | | | | | Previously we were using a B/UB source in an Align16 instruction, which is illegal. It for some reason works on all platforms, except Broadwell. Cc: "10.5" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86811 Reviewed-by: Ian Romanick <[email protected]>
* i965/blorp: Emit MADs.Matt Turner2015-02-192-4/+11
| | | | | | Low hanging fruit: cuts a couple of instructions. Reviewed-by: Ian Romanick <[email protected]>
* i965/blorp: Optimize clamping tex coords.Matt Turner2015-02-192-4/+22
| | | | | | | | | | | Each emit_cond_mov() emits a CMP of its first to arguments using the specified conditional mod, followed by a predicated MOV of the fifth argument into the fourth. In all four cases here, it was just implementing MIN/MAX which we can do in a single SEL instruction. Also reorder the instructions for a slightly better schedule. Reviewed-by: Ian Romanick <[email protected]>
* i965: Use greater-equal cmod to implement maximum.Matt Turner2015-02-194-7/+10
| | | | | | | | The docs specifically call out SEL with .l and .ge as the implementations of MIN and MAX respectively. Among other things, SEL with these conditional mods are commutative. Reviewed-by: Ian Romanick <[email protected]>
* i965: Don't emit saturates for instructions without destinations.Matt Turner2015-02-192-2/+2
| | | | | | | | | | | | We were special casing OPCODE_END but no other instructions that have no destination, like OPCODE_KIL, leading us to emitting MOVs with null destinations. total instructions in shared programs: 5705243 -> 5701539 (-0.06%) instructions in affected programs: 124104 -> 120400 (-2.98%) helped: 904 Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Consider MOV.SAT to interfere if it has a source modifier.Matt Turner2015-02-192-4/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | The saturate propagation pass recognizes that the second instruction below does not interfere with an attempt to propagate the saturate modifier from instruction 3 to 1. 1: add(8) dst0 src0 src1 2: mov.sat(8) dst1 dst0 3: mov.sat(8) dst2 dst0 Unfortunately, we did not consider the case of instruction 2 having a source modifier on dst0. Take for instance: 1: add(8) dst0 src0 src1 2: mov.sat(8) dst1 -dst0 3: mov.sat(8) dst2 dst0 Consider such an instruction to interfere. Increase instruction counts in Anomaly 2, which could be a bug fix depending on the values the first instruction produces. instructions in affected programs: 53228 -> 53934 (1.33%) HURT: 360 Cc: <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Use fs_inst::overwrites_reg() in saturate propagation.Matt Turner2015-02-192-4/+44
| | | | | | | This is safer and matches the conditional_mod propagation pass. Cc: <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Add unit tests for saturate propagation pass.Matt Turner2015-02-192-0/+362
| | | | | Cc: <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Use the without_array predicateTimothy Arceri2015-02-201-5/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* nv50: add PIPELINE_STATISTICS query support, based on nvc0Ilia Mirkin2015-02-193-3/+28
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Tested-by: Nick Tenney <[email protected]>
* svga: add missing :Ilia Mirkin2015-02-191-1/+1
| | | | | Fixes: 924ee3f408 ("gallium: add shader cap for dldexp/dfracexp support") Signed-off-by: Ilia Mirkin <[email protected]>
* nir/GCM: Pull unpinned instructions out of blocks while pinningJason Ekstrand2015-02-191-37/+25
| | | | | | | | This lets us be slightly more efficient by not walking the CFG extra times. Also, it may make it easier to ensure that GVN happens on only unpinned instructions. Reviewed-by: Reviewed-by: Connor Abbott <[email protected]>
* nir/GCM: Use pass_flags instead of bitsets for tracking visited/pinnedJason Ekstrand2015-02-191-46/+49
| | | | Reviewed-by: Reviewed-by: Connor Abbott <[email protected]>
* nir: Add a global code motion (GCM) passJason Ekstrand2015-02-193-0/+504
| | | | | | | | | v2 Jason Ekstrand <[email protected]>: - Use nir_dominance_lca for computing least common anscestors - Use the block index for comparing dominance tree depths - Pin things that do partial derivatives Reviewed-by: Reviewed-by: Connor Abbott <[email protected]>
* nir/instr: Change "live" to a more generic "pass_flags" fieldJason Ekstrand2015-02-192-7/+13
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir: Make nir_[cf_node/instr]_[prev/next] return null if at the endJason Ekstrand2015-02-191-6/+22
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/from_ssa: Don't try to read an invalid instructionJason Ekstrand2015-02-191-1/+1
| | | | | | | | | | | | Right now, the nir_instr_prev function function blindly looks up the previous element in the exec list and casts it to an instruction even if it's the tail sentinel. The next commit will change this to return null if it's the first instruction. Making this change first avoids getting a segfault between commits. The only reason we never noticed is that, thanks to the way things are laid out in nir_block, the casted instruction's type was never parallal_copy. Reviewed-by: Connor Abbott <[email protected]>
* nir/validate: Validate SSA defs the same way we do for registersJason Ekstrand2015-02-191-8/+79
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/validate: Validate if_uses on registersJason Ekstrand2015-02-191-18/+44
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir: Properly clean up CF nodes when we remove themJason Ekstrand2015-02-191-0/+54
| | | | | | | | | | Previously, if you remved a CF node that still had instructions in it, none of the use/def information from those instructions would get cleaned up. Also, we weren't removing if statements from the if_uses of the corresponding register or SSA def. This commit fixes both of these problems Reviewed-by: Connor Abbott <[email protected]>
* nir: use nir_foreach_ssa_def for indexing ssa defsJason Ekstrand2015-02-191-23/+5
| | | | | | | This is both simpler and more correct. The old code didn't properly index load_const instructions. Reviewed-by: Connor Abbott <[email protected]>
* nir/from_ssa: Use the nir_block_dominance function instead of our ownJason Ekstrand2015-02-191-7/+2
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/dominance: Add a constant-time mechanism for comparing blocksJason Ekstrand2015-02-192-0/+39
| | | | | | | | | This is mostly thanks to Connor. The idea is to do a depth-first search that computes pre and post indices for all the blocks. We can then figure out if one block dominates another in constant time by two simple comparison operations. Reviewed-by: Connor Abbott <[email protected]>
* nir/dominance: Expose the dominance intersection functionJason Ekstrand2015-02-192-0/+24
| | | | | | | | | | Being able to find the least common anscestor in the dominance tree is a useful thing that we may want to do in other passes. In particular, we need it for GCM. v2: Handle NULL inputs by returning the other block Reviewed-by: Connor Abbott <[email protected]>
* st/mesa: lower DFRACEXP/DLDEXP when they are not supportedIlia Mirkin2015-02-191-0/+3
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* st/mesa: disable lowering of dops to dfrac when dround is availableIlia Mirkin2015-02-191-7/+6
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* st/mesa: add support for new double opcodesIlia Mirkin2015-02-191-1/+5
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* gallium: add shader cap for dldexp/dfracexp supportIlia Mirkin2015-02-198-0/+10
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* gallium: add a cap to enable double rounding opcodesIlia Mirkin2015-02-198-1/+15
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* gallium: add some more double opcodes to avoid unnecessary loweringIlia Mirkin2015-02-193-1/+50
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* docs/GL3.txt: softpipe now supports GL_ARB_gpu_shader_fp64Dave Airlie2015-02-201-1/+1
| | | | Signed-off-by: Dave Airlie <[email protected]>
* st/mesa: add st fp64 support (v7.1)Dave Airlie2015-02-202-125/+460
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support to the state tracker for ARB_gpu_shader_fp64. The details are explained in comments within the code. v2 : add double to int/unsigned conversion v3: handle fp64 consts better v4: use DRSQ v4.1: add d2b v4.2: drop DDIV v5: split out some prep patches. v5.1: add some comments. v5.2: more comments v6: simplify down the double instruction generation loop. v7: Merge Ilia's two cleanup patches. v7.1: minor fixups for Ilia patch + cleanups Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/st_tgsi_to_glsl: prepare add_constant for fp64Dave Airlie2015-02-201-20/+21
| | | | | | | | This just moves stuff around a little to make the next patch cleaner. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st/glsl_to_tgsi: convert dst to an arrayDave Airlie2015-02-201-65/+65
| | | | | | | | This is just prep work for fp64 support where we need an array of 2 dst values. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: just avoid warnings with fp64Dave Airlie2015-02-205-0/+42
| | | | | | | This just fills in some blanks to avoid warnings in the i965 driver. Reviewed-by: Chris Forbes <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glsl: Add compute to _mesa_shader_stage_to_string(); use unreachable.Kenneth Graunke2015-02-191-2/+2
| | | | | | | | This is basically Ian's review feedback for my patch that added _mesa_shader_stage_to_abbrev() - it just makes both consistent again. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/vec4: Print "VS" or "GS" when compiles fail, not "vec4".Kenneth Graunke2015-02-191-1/+1
| | | | | | | | | | This is now trivial to do right. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/vec4: Replace debug_flag with debug_enabled.Kenneth Graunke2015-02-196-10/+5
| | | | | | | | | | | backend_visitor now handles this, so we can delete the vec4_visitor specific code. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Make scheduler cycle estimates use the proper stage name.Kenneth Graunke2015-02-191-5/+6
| | | | | | | | | | | | | | | Previously, the vec4 backend labeled shaders as "vec4" - now it uses the specific names "VS" and "GS". The FS backend now correctly prints "VS" for vertex shaders (rather than "fs"). It also prints "FS" instead of "fs" for fragment shaders; preserving that behavior didn't seem essential. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Un-hardcode DEBUG_WM, "FS", and "fragment".Kenneth Graunke2015-02-192-7/+8
| | | | | | | | | | These code paths can (or will) be used for other shader stages. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Create backend_visitor fields for debugging messages.Kenneth Graunke2015-02-192-0/+6
| | | | | | | | | | | | | We introduce three new fields in backend_visitor: - debug_enabled: whether or not INTEL_DEBUG & DEBUG_<stage flag> - stage_name: "vertex", "fragment", etc. for use in messages - stage_abbrev: "VS", "FS", etc. for use in messages Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Add a function to translate MESA_SHADER_* into DEBUG_* enums.Kenneth Graunke2015-02-192-0/+15
| | | | | | | | | | | | When compiling, we have a gl_shader_stage (MESA_SHADER_*) enum, and want to know whether debugging is enabled for that stage. This allows us to easily translate it into the corresponding debug flag. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* glsl: Create a _mesa_shader_stage_to_abbrev() function.Kenneth Graunke2015-02-192-0/+20
| | | | | | | | | | | | | This is similar to _mesa_shader_stage_to_string(), but returns "VS" instead of "vertex". v2: Use unreachable() and add MESA_SHADER_COMPUTE (requested by Ian). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Use VARYING_SLOT checks rather than strcmp().Kenneth Graunke2015-02-192-3/+3
| | | | | | | | | | | | | | Comparing the location field is equivalent and more efficient. We'll also need this when we start using NIR for ARB programs, as our NIR converter will set the location field correctly, but probably won't use the GLSL names for these concepts. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Remove type parameter from emit_vs_system_value().Kenneth Graunke2015-02-192-5/+4
| | | | | | | | | | | Every VS system value has type D. We can always add this back if that changes, but for now, it's extra typing. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
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