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* radeonsi: rename enable_s3tc -> enable_compressed_formatsMarek Olšák2015-08-061-5/+4
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: add DRM and LLVM version to the renderer stringMarek Olšák2015-08-062-4/+24
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: always flush framebuffer caches at the beginning of IBsMarek Olšák2015-08-061-1/+2
| | | | | | | better safe than sorry Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: don't count the exact needed CS space if the CS is large enoughMarek Olšák2015-08-061-2/+11
| | | | Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: don't crash when cleaning up after an incomplete contextMarek Olšák2015-08-061-7/+11
| | | | Reviewed-by: Alex Deucher <[email protected]>
* i965: Rename MIPTREE_LAYOUT_ALLOC_* -> MIPTREE_LAYOUT_TILING_*.Matt Turner2015-08-067-20/+20
| | | | | | | | | Ben suggested that I rename MIPTREE_LAYOUT_ALLOC_ANY_TILED since it needed to include no tiling at all, but the name MIPTREE_LAYOUT_ALLOC_ANY is pretty nondescriptive. We can avoid confusion by replacing "ALLOC" with "TILING" in the identifiers. Reviewed-by: Ben Widawsky <[email protected]>
* i965: Correct a mistake that always forced texture tiling.Matt Turner2015-08-061-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Regression since commit 3a31876600, when tiling modes were moved into layout_flags. The relevant enum values are MIPTREE_LAYOUT_ALLOC_YTILED = 1 << 5 MIPTREE_LAYOUT_ALLOC_XTILED = 1 << 6 MIPTREE_LAYOUT_ALLOC_ANY_TILED = MIPTREE_LAYOUT_ALLOC_YTILED | MIPTREE_LAYOUT_ALLOC_XTILED MIPTREE_LAYOUT_ALLOC_LINEAR = 1 << 7 so the expression (layout_flags & MIPTREE_LAYOUT_ALLOC_ANY_TILED) can never produce a value of MIPTREE_LAYOUT_ALLOC_LINEAR. The enum this replaced was enum intel_miptree_tiling_mode { INTEL_MIPTREE_TILING_ANY, INTEL_MIPTREE_TILING_Y, INTEL_MIPTREE_TILING_NONE, }; where "ANY" means "Y" or "NONE" (i.e., linear). As such, remove the unused (and worse, unhandled) MIPTREE_LAYOUT_ALLOC_XTILED and redefine MIPTREE_LAYOUT_ALLOC_ANY_TILED to mean what it did before. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91513 Reviewed-by: Ben Widawsky <[email protected]>
* i965: Request a miptree with no tiling intel_miptree_map_blit().Matt Turner2015-08-061-1/+1
| | | | | | | Regression since commit 3a31876600, when tiling modes were moved into layout_flags. Reviewed-by: Ben Widawsky <[email protected]>
* radeonsi: add a HUD query showing the number of shaders createdMarek Olšák2015-08-064-0/+17
| | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add a HUD query showing the number of compiler invocationsMarek Olšák2015-08-064-1/+19
| | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: display cumulative results for some driver queriesMarek Olšák2015-08-061-2/+4
| | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: switch the buffer-wait-time query to microsecondsMarek Olšák2015-08-062-3/+3
| | | | | | | This display the units in the HUD. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: change some driver query types to HzMarek Olšák2015-08-061-2/+2
| | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium/hud: automatically print % if max_value == 100Marek Olšák2015-08-061-6/+11
| | | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium/hud: fix printing % next to panesMarek Olšák2015-08-061-1/+1
| | | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium/hud: replace assertions with clamping the unit indexMarek Olšák2015-08-061-19/+23
| | | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium,hud: allow displaying cumulative values instead of averageMarek Olšák2015-08-064-8/+36
| | | | | | | | | The cumulative value is useful for queries like the number of shader compilations. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium/hud: fix printing byte unitsMarek Olšák2015-08-061-1/+1
| | | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium,hud: add support for Hz units in driver queriesMarek Olšák2015-08-062-0/+8
| | | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: before storing tess levels, load them from LDS instead of temporaryMarek Olšák2015-08-061-79/+57
| | | | | | | | | Also use only one store if stride <= 4. All the fetches from and stores to temporaries can be removed now. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91461 Reviewed-by: Michel Dänzer <[email protected]>
* winsys/radeon: loosen up the requirements for how much memory IBs can useMarek Olšák2015-08-061-4/+9
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: always use the llvm. prefix in intrinsic namesMarek Olšák2015-08-061-6/+16
| | | | | Acked-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/winsys: increase the IB size for VMMarek Olšák2015-08-064-6/+17
| | | | | | | Luckily, there is a kernel query, so use the size from that. It currently returns 256KB. It can be increased in the kernel. Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: allow the winsys to choose the IB sizeMarek Olšák2015-08-0611-18/+18
| | | | | | | Picked from the amdgpu branch. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: suspend timer queries between IBsMarek Olšák2015-08-065-25/+66
| | | | | | | When we are measuring the time spent in a draw call, an unexpected flush can distort the result. Reviewed-by: Michel Dänzer <[email protected]>
* st/mesa: implement DrawTransformFeedbackStreamMarek Olšák2015-08-063-31/+34
| | | | Reviewed-by: Dave Airlie <[email protected]>
* mesa: save which transform feedback buffer is associated with which streamMarek Olšák2015-08-062-0/+6
| | | | Reviewed-by: Dave Airlie <[email protected]>
* vbo: pass the stream from DrawTransformFeedbackStream to driversMarek Olšák2015-08-0619-26/+39
| | | | Reviewed-by: Dave Airlie <[email protected]>
* mesa: handle no-op cases sooner in _mesa_[Client]ActiveTexture()Brian Paul2015-08-061-10/+10
| | | | | | | If the new texture unit is the current texture unit, we can return before error checking. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Lower arithmetic instructions with register regions of unsupported ↵Francisco Jerez2015-08-061-0/+62
| | | | | | | | | | | | | | | | | | | | | | width. This extends the SIMD lowering pass to enforce the hardware limitation that no directly-addressed source may read more than 2 physical GRFs. One can easily go over this limit when doing 64-bit arithmetic (e.g. FP64 or extended-precision integer MULs) or SIMD32, so it's nice to be able to just emit an instruction of the intended execution size from the visitor and let the lowering pass deal with this restriction transparently. Some hardware arithmetic instructions are not handled here, including all instructions that use the accumulator implicitly (which the SIMD lowering pass deliberately doesn't handle), instructions with non-per-channel sources (e.g. LINE or PLANE) and SEND-like instructions, which need special handling most likely as virtual opcodes. Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Fix fs_inst::regs_read() for sources in the ATTR file.Francisco Jerez2015-08-061-0/+1
| | | | | | | | | | | Otherwise it would crash on Gen8 with scalar VS. The issue can easily be reproduced with the following patch, but I don't see any reason why it wouldn't be possible to end up with an ATTR argument here even without it. CC: [email protected] Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Implement nir_op_imul/umul_high in terms of MULH.Francisco Jerez2015-08-061-31/+2
| | | | | | And get rid of another no16() call. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Lower the MULH virtual instruction.Francisco Jerez2015-08-061-0/+55
| | | | | | | | | | | | Translate MULH into the MUL/MACH sequence. This does roughly the same thing that nir_emit_alu() used to do but we can now handle 16-wide by taking advantage of the SIMD lowering pass. The force_sechalf workaround near the bottom is required because the SIMD lowering pass will emit instructions with non-zero quarter control and we need to make sure we avoid that on integer arithmetic instructions with implicit accumulator access due to a known hardware bug on IVB. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Indent the implementation of 32x32-bit MUL lowering by one level.Francisco Jerez2015-08-061-130/+134
| | | | | | | | | In order to make room for the code that will lower the MULH virtual instruction. Also move the hardware generation and execution type checks into the same branch, they are going to have to be different for MULH. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Lower 32x32 bit multiplication on BXT.Francisco Jerez2015-08-061-2/+2
| | | | | | | AFAIK BXT has the same annoying alignment limitation as CHV on the source register regions of 32x32 bit MULs, give it the same treatment. Reviewed-by: Matt Turner <[email protected]>
* i965: Define virtual instruction to calculate the high 32 bits of a multiply.Francisco Jerez2015-08-066-0/+13
| | | | | | | | | | | This instruction will translate to the MUL/MACH sequence that computes the high 32-bits of the result of a 64-bit multiply. Before Gen8 integer operations that used the accumulator were limited to 8-wide, but the SIMD lowering pass can easily be hooked up to sidestep this limitation, we just need a virtual opcode to represent the MUL/MACH sequence in the IR. Reviewed-by: Matt Turner <[email protected]>
* glsl: Initialize patch member of glsl_struct_fieldMichel Dänzer2015-08-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is apparently a subtle difference in C++ between F f; and F f(); The former will use the default constructor. If there is no default constructor specified, the compiler provides one that simply invokes the default constructor for each field. For built-in basic types, the default constructor does nothing. The later will, according to http://stackoverflow.com/questions/2417065/does-the-default-constructor-initialize-built-in-types) perform value-initialization of the type. For built-in types this means initializing to zero. The per_vertex_accumulator constructor is: per_vertex_accumulator::per_vertex_accumulator() : fields(), num_fields(0) { } This is the second form of constructor, so the glsl_struct_field objects were previously zero initialized. With the addition of an empty default constructor in commit 7ac946e5, per_vertex_accumulator::fields receive no initialization. Fixes a bunch of random (mostly tessellation related) piglit failures since commit 7ac946e5 ("glsl: Add constuctors for the common cases of glsl_struct_field"). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91544 Reviewed-by: Ian Romanick <[email protected]>
* nir: add missing type to type_size_vec4()Timothy Arceri2015-08-051-0/+2
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa: Add missing check of format and type in glTexSubImageXD on GLES 3.0Eduardo Lima Mitev2015-08-051-47/+69
| | | | | | | | | | | | | | | | Argument validation for glTexSubImageXD is missing a check of format and type against texture object's internal format when profile is OpenGL-ES 3.0+. This patch also groups together all format and type checks on GLES into a new function texture_format_error_check_gles(), to factorize similar code in texture_format_error_check(). Fixes 2 dEQP tests: * dEQP-GLES3.functional.negative_api.texture.texsubimage2d * dEQP-GLES3.functional.negative_api.texture.texsubimage3d Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Fix error returned by glCopyTexImage2D() upon an invalid internal formatEduardo Lima Mitev2015-08-051-9/+9
| | | | | | | | | | | | | | | | | | | | | | | Page 161 of the OpenGL-ES 3.1 (PDF) spec, and page 207 of the OpenGL 4.5 (PDF), both on section '8.6. ALTERNATE TEXTURE IMAGE SPECIFICATION COMMANDS', states: "An INVALID_ENUM error is generated if an invalid value is specified for internalformat". It is currently returning INVALID_OPERATION error because _mesa_get_read_renderbuffer_for_format() is called before the internalformat argument has been validated. To fix this, we move this call down the validation process, after _mesa_base_tex_format() has been called. _mesa_base_tex_format() effectively serves as a validator for the internal format. Fixes 1 dEQP test: * dEQP-GLES3.functional.negative_api.texture.copyteximage2d_invalid_format Fixes 1 piglit test: * spec@oes_compressed_etc1_rgb8_texture@basic Reviewed-by: Ian Romanick <[email protected]> Cc: 10.6 <[email protected]>
* mesa: Validate target before resolving tex obj in glTex(ture)SubImageXDEduardo Lima Mitev2015-08-051-15/+14
| | | | | | | | | | | | | | | Currently, glTexSubImageXD attempt to resolve the texture object (by calling _mesa_get_current_tex_object()) before validating the given target. However, that method explicitly states that target must have been validated before calling it, so it never returns a user error. The target validation occurs later when texsubimage_error_check() is called. This patch reorganizes target validation, taking it out from the error check function and into a point before the texture object is resolved. Reviewed-by: Ian Romanick <[email protected]> Cc: 10.6 <[email protected]>
* mesa: Fix errors values returned by glShaderBinary()Eduardo Lima Mitev2015-08-051-3/+14
| | | | | | | | | | | | | | | | | Page 68, section 7.2 'Shader Binaries" of the of the OpenGL ES 3.1, and page 88 of the OpenGL 4.5 specs state: "An INVALID_VALUE error is generated if count or length is negative. An INVALID_ENUM error is generated if binaryformat is not a supported format returned in SHADER_BINARY_FORMATS." Currently, an INVALID_OPERATION error is returned for all cases. Fixes 1 dEQP test: * dEQP-GLES3.functional.negative_api.shader.shader_binary Reviewed-by: Ian Romanick <[email protected]> Cc: 10.6 <[email protected]>
* mesa: do not modify args when errors with GetProgramResourceNameTapani Pälli2015-08-051-6/+0
| | | | | | | | | | | | Original purpose of these lines was to be more friendly against GUI tools using the extension. However conformance suite explicitly checks that buffers are not modified in error conditions. Fixes: ES31-CTS.program_interface_query.buff-length Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* glsl: add variable mode check to build_stagerefTapani Pälli2015-08-051-4/+13
| | | | | | | | | | | | | Currently stage reference mask is built using the variable name only. However it can happen that input of one stage has same name as output from another stage. Adding check of variable mode makes sure we do not pick wrong variable. Fixes some subcases from ES31-CTS.program_interface_query.no-locations Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* dri: set the __DRI_API_OPENGL bit based on max gl compat versionFrank Binns2015-08-041-1/+3
| | | | | | | | This matches similar behaviour for the __DRI_API_OPENGL_CORE bit. Signed-off-by: Frank Binns <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* egl: Add eglQuerySurface surface type check for EGL_LARGEST_PBUFFER attribFrank Binns2015-08-041-1/+2
| | | | | | | | | | | | | | | | | | | Calling eglQuerySurface on a window or pixmap with the EGL_LARGEST_PBUFFER attribute resulted in the contents of the 'value' parameter being modified. This is the wrong behaviour according to the EGL spec, which states: "Querying EGL_LARGEST_PBUFFER for a pbuffer surface returns the same attribute value specified when the surface was created with eglCreatePbufferSurface. For a window or pixmap surface, the contents of value are not modified." Avoid this from happening by checking that the surface type is EGL_PBUFFER_BIT before modifying the contents of the parameter. Cc: <[email protected]> Signed-off-by: Frank Binns <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* egl/dri: Add error info needed for EGL_EXT_image_dma_buf_import extensionFrank Binns2015-08-042-2/+10
| | | | | | | | | | | | | Update the DRI image interface error codes to reflect the needs of the EGL_EXT_image_dma_buf_import extension. This means updating the existing error code documentation and adding a new __DRI_IMAGE_ERROR_BAD_ACCESS error code so that drivers can correctly reject unsupported pitches and offsets. Hook the new error code up in EGL to return EGL_BAD_ACCESS. Cc: <[email protected]> Signed-off-by: Frank Binns <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* vc4: Use nir_lower_load_const_to_scalar().Eric Anholt2015-08-041-0/+1
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* nir: Add a nir_lower_load_const_to_scalar() pass.Eric Anholt2015-08-043-0/+105
| | | | | | | | This is useful to increase the CSE opportunities for a scalar backend. It avoids regressions when dropping vc4's custom CSE implementation. v2: Cleanups by Matt (decl in the for loop, and unreachable()). Reviewed-by: Matt Turner <[email protected]>
* vc4: Don't bother de-SSAing values that aren't part of phi webs.Eric Anholt2015-08-041-15/+44
| | | | We can just support them the same way we do load_const's SSA values.
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