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* i965/fs: take into account doubles when calculating read_size for MOV_INDIRECTSamuel Iglesias Gonsálvez2016-05-101-2/+3
| | | | | | | | | v2: - Fix assert's line width (Topi). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fs: demote_pull_constants() did not take into account double typesSamuel Iglesias Gonsálvez2016-05-101-1/+8
| | | | | | | | | | | The constants could be double, and it was allocating size for float types for the destination register of varying pull constant loads. Then the fs_visitor::validate() will complain. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fs: push first double-based uniforms in push constant bufferSamuel Iglesias Gonsálvez2016-05-101-30/+82
| | | | | | | | | | | | | | | | | | | | | When there is a mix of definitions of uniforms with 32-bit or 64-bit data type sizes, the driver ends up doing misaligned access to double based variables in the push constant buffer. To fix this, this patch pushes first all the 64-bit variables and then the rest. Then, all the variables would be aligned to its data type size. v2: - Fix typo and improve comment (Jordan). - Use ralloc(NULL,...) instead of rzalloc(mem_ctx,...) (Jordan). - Fix typo (Topi). - Use pointers instead of references in set_push_pull_constant_loc() (Topi). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: recognize writes with a subreg_offset > 0 as partialIago Toral Quiroga2016-05-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | Usually, writes to a subreg_offset > 0 would also have a stride > 1 and we would recognize them as partial, however, there is one case where this does not happen, that is when we generate code for 64-bit imemdiates in gen7, where we produce something like this: mov(8) vgrf10:UD, <low 32-bit> mov(8) vgrf10+0.4:UD, <high 32-bit> and then we use the result with a stride of 0, as in: mov(8) vgrf13:DF, vgrf10<0>:DF Although we could try to avoid this issue by producing different code for this by using writes with a stride of 2, that runs into other problems affecting gen7 and the fact is that any instruction that writes to a subreg_offset > 0 is a partial write so we should really recognize them as such. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs/lower_simd_width: Fix registers written for split instructionsIago Toral Quiroga2016-05-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | When the original instruction had a stride > 1, the combined registers written by the split instructions won't amount to the same register space written by the original instruction because the split instructions will use a stride of 1. The current code assumed otherwise and computed the number of registers written by split instructions as an equal share based on the relation between the lowered width and the original execution size of the instruction. It is only after the split, when we interleave the components of the result from the lowered instructions back into the original dst register, that the original stride takes effect and we write all the registers specified by the original instruction. Just make the number of register written the same as the vgrf space we allocate for the dst of the split instruction. Fixes crashes in fp64 tests produced as a result of assigning incorrectly the number of registers written by split instructions, which led to incorrect validation of the size of the writes against the allocated vgrf space. Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: rename our lower_d2f pass to lower_d2xIago Toral Quiroga2016-05-104-4/+4
| | | | | | | Since it no longer handles conversions from double to float but from double to various other 32-bit types. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: implement i2d and u2dIago Toral Quiroga2016-05-101-0/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: implement d2i and d2uIago Toral Quiroga2016-05-102-1/+5
| | | | | | | These need the same treatment as d2f, so generalize our d2f lowering to cover these too. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: implement d2bIago Toral Quiroga2016-05-101-0/+13
| | | | | | v2: Use subscript() instead of stride() (Curro) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: implement fsign() for doublesIago Toral Quiroga2016-05-101-17/+76
| | | | | | | | | | v2 (Sam): - Fix indentation (Kenneth) - Simplify code (Kenneth) v3: Use subscript() instead of stride() (Curro) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: add null_reg_dfIago Toral Quiroga2016-05-101-0/+7
| | | | | | | | Probably not needed since we fix the dst type of comparisons automatically, but for consistency with the rest of null_reg_* functions. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: We only support 32-bit integer ALU operations for nowIago Toral Quiroga2016-05-101-3/+29
| | | | | | | Add asserts so we remember to address this when we enable 64-bit integer support, as suggested by Connor and Jason. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: handle fp64 opcodes in brw_do_channel_expressionsIago Toral Quiroga2016-05-101-9/+14
| | | | | | | | | | | | | | In the case of the pack opcode we are already doing the lowering in NIR, so no need to do it here. The unpack opcode operates on scalars, so it should not be lowered. In the case of frexp_sig and frexp_exp, they are lowered in lower_instructions, so we don't have to care about them. All the remaining opcodes involve conversions from and to doubles and are business as usual. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: add support for f2d and d2fConnor Abbott2016-05-101-0/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: add a pass for legalizing d2fConnor Abbott2016-05-104-0/+81
| | | | | | | | | We need to do this late, in order to avoid partial writes during the optimization loop. v2: Use subscript() instead of stride(). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: fix dst width calculation in CSEConnor Abbott2016-05-101-1/+2
| | | | | | | | v2 (Sam): - Fix line width (Topi). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fs: fix regs_written in LOAD_PAYLOAD for doublesConnor Abbott2016-05-101-2/+6
| | | | | | | | v2: Account for the stride of the dst (Iago) Signed-off-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fs: fix is_copy_payload() for doublesConnor Abbott2016-05-101-1/+1
| | | | | | | | | v2 (Sam): - LOAD_PAYLOAD treats each header source as a 32B block regardless of the datatype. Drop the change (Curro) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fs: fix compares for doublesConnor Abbott2016-05-101-3/+31
| | | | | | | | | | | | The destination has to have the same source as the type, or else the simulator will complain. As a result, we need to emit a CMP that outputs a 64-bit wide result and then do a strided MOV to pick out the low 32 bits of each channel. v2: Use subscript() instead of stride() (Curro) Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: extend exec_size halving in the generatorConnor Abbott2016-05-101-6/+10
| | | | | | | | | | | | | The HW has a restriction that only vertical stride may cross register boundaries. Previously, this only mattered for SIMD16 instructions where we needed to use the same regioning parameters as the equivalent SIMD8 instruction but double the exec size. But we need to do the same splitting for 64-bit instructions as well as instructions with a stride of 2 (which effectively consume 64 bits per element). Fix up the code to do the right thing instead of special-casing SIMD16. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: fix assign_constant_locations() for doublesConnor Abbott2016-05-101-2/+6
| | | | | | | | | | | | | Uniform doubles will read two registers, in which case we need to mark both as being live. v2 (Sam): - Use a formula to get the number of registers read with proper units (Curro). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: use byte_offset() in offset() for uniformsConnor Abbott2016-05-101-3/+1
| | | | | | | | This makes things more consistent, and also fixes the offset calculation for double uniforms. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: handle uniforms in byte_offset()Connor Abbott2016-05-101-1/+5
| | | | | | | | v2: Do it only for uniforms (Iago) Signed-off-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: fix type_size() for doublesConnor Abbott2016-05-101-1/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: optimize unpack doubleIago Toral Quiroga2016-05-101-4/+26
| | | | | | | | | | | | When we are actually unpacking from a double that we have previously packed from its 32-bit components we can bypass the pack operation and source from its arguments directly. v2 (Sam): - Fix line overflow (Topi) - Bail if the parent instruction's source is not SSA (Connor) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: optimize pack doubleIago Toral Quiroga2016-05-101-0/+29
| | | | | | | | | | | | | | When we are actually creating a double using values obtained from a previous unpack operation we can bypass the unpack and source from the original double value directly. v2: - Style changes (Topi) - Bail is parent instruction's src is not SSA (Connor) v3: Use subscript() instead of stride() (Curro) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs/nir: translate double pack/unpackConnor Abbott2016-05-101-0/+12
| | | | | | | | | v2 (Sam): - Fix line overflow (Topi). v3: Use subscript() instead of stride() (Curro) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: add a pass for lowering PACK opcodesConnor Abbott2016-05-104-0/+62
| | | | | | v2: Use subscript() instead of stride() (Curro) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: add PACK opcodeConnor Abbott2016-05-105-1/+15
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Introduce helper to extract a field from each channel of a register.Francisco Jerez2016-05-101-0/+28
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: always pass the bitsize to brw_type_for_nir_type()Connor Abbott2016-05-101-3/+9
| | | | | | | | | | v2 (Sam): - Add bitsize to brw_type_for_nir_type() in optimize_extract_to_float() v3 (Sam): - Fix line width (Topi). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: add support for printing double immediatesConnor Abbott2016-05-101-0/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: don't propagate 64-bit immediatesConnor Abbott2016-05-101-0/+2
| | | | | | | | | They can only be used with 1-src instructions, which practically (since we should've constant-propagated away all 1-src instructions with 64-bit immediates in NIR) means that they must be kept in separate MOV's and can't be propagated. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: use the NIR bit size when creating registersConnor Abbott2016-05-101-8/+28
| | | | | | | | | | | | | | | | | | | | | v2 (Iago): - Squashed bits from 'support double precission constant operands for the implementation of 64-bit emit_load_const'. - Do not use BRW_REGISTER_TYPE_D for all 32-bit registers since that breaks asserts and functionality for some piglit tests. Just keep 32-bit types untouched and add 64-bit support. - Use DF instead of Q for 64-bit registers. Otherwise the code we generate will use Q sometimes and DF others and we hit unwanted DF/Q conversions, so always use DF. v3 (Sam): - Mark 'reg_type' occurrences as const (Topi). Signed-off-by: Topi Pohjolainen <[email protected]> Signed-off-by: Tapani Palli <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]> Signed-off-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: fixup uniform setup for doublesConnor Abbott2016-05-101-1/+6
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: two-argument instructions can only use 32-bit immediatesIago Toral Quiroga2016-05-101-0/+2
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: fix brw_abs_immediate() for doublesIago Toral Quiroga2016-05-101-2/+4
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: fix brw_saturate_immediate() for doublesIago Toral Quiroga2016-05-101-6/+27
| | | | | | | | | | v2 (Sam): - Mark 'size' as const (Topi). - Add comment to explain that we do copies 64-bits regardless of the type (Topi) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: fix is_zero(), is_one() and is_negative_one() for doublesConnor Abbott2016-05-101-4/+24
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: fix brw_negate_immediate() for doublesConnor Abbott2016-05-101-2/+4
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/eu: add support for DF immediatesConnor Abbott2016-05-101-7/+21
| | | | | | | | | v2 (Sam): - Remove 'however' from the comment (Topi) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: add support for disassembling DF immediatesConnor Abbott2016-05-101-1/+1
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: add support for getting/setting DF immediatesConnor Abbott2016-05-101-0/+25
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: add brw_imm_dfConnor Abbott2016-05-102-0/+10
| | | | | | | | | | v2 (Iago) - Fixup accessibility in backend_reg Signed-off-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/eu: Allow 3-src float ops with doublesTopi Pohjolainen2016-05-101-6/+18
| | | | | | | | | | v2: - set 3src_src_type for BRW_REGISTER_TYPE_DF (Connor) Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/disasm: fix disasm of 3-src doublesConnor Abbott2016-05-101-0/+1
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Tell backend register about double precision typeTopi Pohjolainen2016-05-101-1/+2
| | | | | | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Signed-off-by: Tapani P\344lli <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Determine size of double precision float registerTopi Pohjolainen2016-05-101-0/+1
| | | | | | | | | | | | | | This is used to determine how many registers an instruction reads and writes as well as for offseting register region into a desired component. v2 (Connor): rebase on master Signed-off-by: Topi Pohjolainen <[email protected]> Signed-off-by: Tapani P\344lli <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Lower DFRACEXP/DLDEXPTopi Pohjolainen2016-05-101-0/+1
| | | | | | | | | | | | v2 (Connor): rebase on master which moved this to brw_link.cpp v3 (Sam): - Only enable DFREXP_DLDEXP_TO_ARITH in process_glsl_ir(). This is used for doubles. Single floating point op is lowered by NIR. Signed-off-by: Topi Pohjolainen <[email protected]> Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: use pack/unpackDouble loweringConnor Abbott2016-05-101-0/+1
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
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