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* nv50: turn samples counts off during blitSamuel Pitoiset2015-07-201-0/+11
* nv50: add nesting support for occlusion queriesSamuel Pitoiset2015-07-202-11/+20
* i965/nir/fs: removed unneeded support for global variablesAlejandro Piñeiro2015-07-203-14/+4
* nv50: fix max level clamping on G80Ilia Mirkin2015-07-201-2/+9
* gm107/ir: fix indirect txq emissionIlia Mirkin2015-07-181-2/+8
* nvc0/ir: don't worry about sampler in txq handlingIlia Mirkin2015-07-181-22/+8
* nvc0/ir: fix txq on indirect samplersIlia Mirkin2015-07-182-2/+56
* i965: Disable resource streamer in BLORPAbdiel Janulgue2015-07-181-0/+2
* i965: Upload binding tables in hw-generated binding table format.Abdiel Janulgue2015-07-181-9/+57
* i965: Implement interface to edit binding table entriesAbdiel Janulgue2015-07-182-0/+64
* i965: Enable hardware-generated binding tables on render path.Abdiel Janulgue2015-07-188-4/+128
* i965: Enable resource streamer for the batchbufferAbdiel Janulgue2015-07-187-2/+36
* i965: Define HW-binding table and resource streamer control opcodesAbdiel Janulgue2015-07-182-0/+33
* vc4: Switch to using a separate ioctl for making shaders.Eric Anholt2015-07-174-12/+78
* mesa: fix up some texture error checksRoland Scheidegger2015-07-182-21/+21
* vc4: Fix printing of shader-db debug when shader-db isn't turned on.Eric Anholt2015-07-171-4/+6
* vc4: Add debugging on texture relocation validation failures.Eric Anholt2015-07-171-7/+13
* vc4: Also consider uniform 0 in uniform lowering.Eric Anholt2015-07-171-3/+3
* vc4: Use the pure/const attributes on a bunch of our QPU functions.Eric Anholt2015-07-172-18/+18
* mesa: Detect and provide macros for function attributes pure and const.Eric Anholt2015-07-172-0/+22
* i965/fs: don't make unused payload registers interfereConnor Abbott2015-07-171-1/+6
* i965/fs: remove special case in setup_payload_interference()Connor Abbott2015-07-171-20/+0
* i965/fs: Mark last used ip for all regs read in the payloadJordan Justen2015-07-171-1/+4
* i965/fs: fix regs_read() for LINTERPConnor Abbott2015-07-171-1/+2
* nir: add nir_foreach_instr_safe_reverse()Connor Abbott2015-07-171-0/+2
* nir: add nir_instr_is_first() and nir_instr_is_last() helpersConnor Abbott2015-07-171-0/+12
* i965/cs: Use dispatch width of 8 for cs terminate payload setupJordan Justen2015-07-161-1/+1
* i965/cs: Return 1 for regs_read on CS_OPCODE_CS_TERMINATEJordan Justen2015-07-161-0/+3
* program: Allow redundant OPTION ARB_fog_* directives.Kenneth Graunke2015-07-161-13/+37
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-167-47/+51
* Revert "i965: Push miptree tiling request into flags"Ben Widawsky2015-07-167-51/+47
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-167-47/+51
* i965/fs: Factor out universally broken calculation of the register component ...Francisco Jerez2015-07-164-12/+23
* i965: Implement nir_op_uadd_carry and _usub_borrow without accumulator.Francisco Jerez2015-07-163-35/+12
* i965: Implement b2f and b2i using negation.Francisco Jerez2015-07-162-9/+2
* gallium: add interface for writable shader buffersMarek Olšák2015-07-162-0/+28
* gallium: add interface for writable shader imagesMarek Olšák2015-07-1610-27/+120
* gallium: add new limits for shader buffers and imagesMarek Olšák2015-07-163-4/+5
* gallium: add BIND flags for R/W buffers and imagesMarek Olšák2015-07-167-13/+19
* gallium: add PIPE_CAP_MAX_SHADER_PATCH_VARYINGSMarek Olšák2015-07-1615-0/+18
* i965/gen9: Use custom MOCS entries set up by the kernel.Francisco Jerez2015-07-162-7/+7
* clover: little OpenCL status code logging cleanEdB2015-07-165-25/+32
* glsl: avoid compiler's segfault when processing operators with void argumentsRenaud Gaubert2015-07-162-2/+16
* r200: fix some potential big endian issuesRoland Scheidegger2015-07-165-129/+140
* radeon: fix some potential big endian issuesRoland Scheidegger2015-07-164-90/+76
* radeon/r200: mark state atoms as dirty after blitsRoland Scheidegger2015-07-162-0/+24
* r200: fix fbo rendering by disabling optimized texture format chooserRoland Scheidegger2015-07-161-1/+13
* i965: Fix 32 bit build warnings in intel_get_yf_ys_bo_size()Anuj Phogat2015-07-151-3/+3
* i965: Optimize batchbuffer macros.Matt Turner2015-07-156-42/+70
* i965: Add and use USED_BATCH macro.Matt Turner2015-07-156-22/+25
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