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* docs: add sha256 checksums for 18.0.3Juan A. Suarez Romero2018-05-071-0/+106
| | | | | Signed-off-by: Juan A. Suarez Romero <[email protected]> (cherry picked from commit 6dc2658fd66c18239ad33cb1ffbdfc22b0d9e51e)
* intel/genxml: Fix a few invalid field widthsChris Wilson2018-05-076-28/+28
| | | | | | | | | | A couple of typos found by inspecting field.end - field.start, revealed a few wide integers declared as bool and some that ended before they started. Cc: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* swr/rast: Fix include for createInstructionCombiningPass with llvm-7.0.Vinson Lee2018-05-051-0/+1
| | | | | | | | | | | | | | | Fix build error after llvm-7.0.0svn r330669 ("InstCombine: Fix layering by not including Scalar.h in InstCombine"). CXX rasterizer/jitter/libmesaswr_la-blend_jit.lo rasterizer/jitter/blend_jit.cpp:816:20: error: use of undeclared identifier 'createInstructionCombiningPass'; did you mean 'createInstructionSimplifierPass'? passes.add(createInstructionCombiningPass()); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ createInstructionSimplifierPass Suggested-by: George Kyriazis <[email protected]> Signed-off-by: Vinson Lee <[email protected]> Reviewed-By: George Kyriazis <[email protected]>
* clover: Add explicit virtual destructor to argument classJan Vesely2018-05-051-0/+1
| | | | | | | | | | It is needed to destroy the v vector in scalar_argument Fixes memory leaks on parameter set/bind. v2: Drop redundant sclara_argument destructor Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* anv/device: expose shaderInt16 support in gen8+Iago Toral Quiroga2018-05-051-1/+1
| | | | | | | | This rollbacks the revert of this patch introduced with commit 7cf284f18e6774c810ed6db17b98e597bf96f8a5. Tested-by: Mark Janes <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compiler: handle conversion to smaller type in the lowering pass for thatIago Toral Quiroga2018-05-052-12/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This rollbacks the revert of this same patch introduced in commit 7b9c15628aae8729118b648f5f473e6ac926b99b. And also squahes the following patch to prevent a piglit regression caused by this change: intel/compiler: Fix lower_conversions for 8-bit types. Author: Jose Maria Casanova Crespo <[email protected]> For 8-bit types the execution type is word. A byte raw MOV has 16-bit execution type and 8-bit destination and it shouldn't be considered a conversion case. So there is no need to change alignment and enter in lower_conversions for these instructions. Fixes a regresion in the piglit test "glsl-fs-shader-stencil-export" that is introduced with this patch from the Vulkan shaderInt16 series: 'i965/compiler: handle conversion to smaller type in the lowering pass for that'. The problem is caused because there is already a case in the driver that injects Byte instructions like this: mov(8) g127<1>UB g2<32,8,4>UB And the aforementioned pass was not accounting for the special handling of the execution size of Byte instructions. This patch fixes this. v2: (Jason Ekstrand) - Simplify is_byte_raw_mov, include reference to PRM and not consider B <-> UB conversions as raw movs. v3: (Matt Turner) - Indentation style fixes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106393 Tested-by: Mark Janes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: handle 16-bit to 64-bit conversions in BSW platformsIago Toral Quiroga2018-05-051-4/+4
| | | | | | | | | | | | | | | | | These are subject to the general restriction that anything that is converted to 64-bit needs to be aligned to 64-bit. We had this already in place for 32-bit to 64-bit conversions, so this patch generalizes the implementation to take effect on any conversion to 64-bit from a source smaller than 64-bit. Fixes assembly validation errors in the following CTS tests in BSW: dEQP-VK.spirv_assembly.instruction.compute.sconvert.int16_to_int64 dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint16_to_uint64 dEQP-VK.spirv_assembly.instruction.compute.sconvert.int16_to_uint64 Tested-by: Mark Janes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: recognize 0x, 0o and 0b when setting default valueCaio Marcelo de Oliveira Filho2018-05-041-1/+2
| | | | | | | | | | | | | Remove the need of converting values that are documented in hexadecimal. This patch would allow writing <field name="3D Command Sub Opcode" ... default="0x1B"/> instead of <field name="3D Command Sub Opcode" ... default="27"/> Reviewed-by: Lionel Landwerlin <[email protected]>
* r200: Enable NV_fog_distanceIan Romanick2018-05-041-0/+1
| | | | | | | With the previous fixes in place, it appears to just work. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Enable NV_fog_distanceIan Romanick2018-05-041-0/+1
| | | | | | | With the previous fixes in place, it appears to just work. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* ffvertex: Don't try to read output registers in fog calculationIan Romanick2018-05-041-4/+6
| | | | | | | | | Gallium drivers use _mesa_remove_output_reads() via st_program to lower output reads away. It seems better to just generate the right thing in the first place. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)Ian Romanick2018-05-041-0/+1
| | | | | | | | Found by inspection, so I made a piglit test too. Signed-off-by: Ian Romanick <[email protected]> Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Silence an unused parameter warningIan Romanick2018-05-041-5/+4
| | | | | | | | | | | main/framebuffer.c: In function ‘update_color_draw_buffers’: main/framebuffer.c:629:46: warning: unused parameter ‘ctx’ [-Wunused-parameter] update_color_draw_buffers(struct gl_context *ctx, struct gl_framebuffer *fb) ^~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/main/readpix: Correct handling of packed floating point valuesGert Wollny2018-05-041-2/+4
| | | | | | | | | | | | | | Make sure that clamping in the pixel transfer operations is enabled/disabled for packed floating point values just like it is done for single normal and half precision floating point values. This fixes a series of CTS tests with virgl that use r11f_g11f_b10f buffers as target, and where virglrenderer reads these surfaces back using the format GL_UNSIGNED_INT_10F_11F_11F_REV. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* util/set: add a set_clear functionScott D Phillips2018-05-042-0/+26
| | | | | | | Clear a set back to the state of having zero entries. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* egl: add EGL_BAD_MATCH error case for surfaceless and androidTapani Pälli2018-05-042-2/+6
| | | | | | | | Just like is done for other backends when suitable config is not found (added in fd4eba4929). Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Juan A. Suarez <[email protected]>
* amd/common: use llvm.amdgcn.wqm for explicit derivativesNicolai Hähnle2018-05-041-0/+7
| | | | | | | To comply with an upcoming change in LLVM, see https://reviews.llvm.org/D46051 Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nv50/ir: fix printing of pixldRhys Perry2018-05-031-1/+1
| | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* st/va: Support YUV formats in vaCreateSurfacesDrew Davenport2018-05-031-23/+36
| | | | Reviewed-by: Kristian H. Kristensen <[email protected]>
* Revert "anv/device: expose shaderInt16 support in gen8+"Mark Janes2018-05-031-1/+1
| | | | | | | This reverts commit 0ba0ac815e078185c1f408ec7078fd1efac1a634. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106393 Reviewed-by: Scott D Phillips <[email protected]>
* Revert "i965/compiler: handle conversion to smaller type in the lowering ↵Mark Janes2018-05-032-7/+12
| | | | | | | | | pass for that" This reverts commit 96b51537908cd2aace85f54b437eeb72e6346b7e. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106393 Reviewed-by: Scott D Phillips <[email protected]>
* swr/rast: Fix WriteBitcodeToFile usage with llvm-7.0.Vinson Lee2018-05-031-0/+4
| | | | | | | | | | | | | | Fix build error after llvm-7.0svn r325155 ("Pass a reference to a module to the bitcode writer."). CXX rasterizer/jitter/libmesaswr_la-JitManager.lo rasterizer/jitter/JitManager.cpp:548:30: error: reference to type 'const llvm::Module' could not bind to an lvalue of type 'const llvm::Module *' llvm::WriteBitcodeToFile(M, bitcodeStream); ^ Suggested-by: George Kyriazis <[email protected]> Signed-off-by: Vinson Lee <[email protected]> Reviewed-By: George Kyriazis <[email protected]>
* egl/x11: Send invalidate to driver on copy_region path in swap_bufferDeepak Rawat2018-05-031-10/+13
| | | | | | | | | | | | | | | | Similar to swap_available path send invalidate to the driver because egl/X11 is not watching for for server's invalidate events. The dri2_copy_region path is trigerred when server supports DRI2 version minor 1. Tested with piglit egl tests for regression. V2: Move invalidate from dri2_copy_region to swap_buffer common. Cc: <[email protected]> Signed-off-by: Deepak Rawat <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* egl: check if colorspace/surface type is supportedJuan A. Suarez Romero2018-05-034-0/+21
| | | | | | | | | | | | | | | | | | According to EGL 1.4 spec, section 3.5.1 ("Creating On-Screen Rendering Surfaces"), if config does not support the colorspace or alpha format attributes specified in attrib_list (as defined for eglCreateWindowSurface), an EGL_BAD_MATCH error is generated. This fixes dEQP-EGL.functional.wide_color.*_888_colorspace_srgb (still not merged, https://android-review.googlesource.com/c/platform/external/deqp/+/667322), which is crashing when trying to create a windows surface with RGB888 configuration and sRGB colorspace. v2: Handle the fix in other backends (Tapani) Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* anv/device: expose shaderInt16 support in gen8+Iago Toral Quiroga2018-05-031-1/+1
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* anv/pipeline: support SpvCapabilityInt16 in gen8+Iago Toral Quiroga2018-05-031-0/+1
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/spirv: add implementation to check for SpvCapabilityInt16 supportIago Toral Quiroga2018-05-032-1/+4
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: implement 16-bit pack/unpack opcodesIago Toral Quiroga2018-05-031-0/+10
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/spirv: implement 16-bit bitcastsIago Toral Quiroga2018-05-031-9/+22
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/lower_64bit_packing: rename the pass to be more genericIago Toral Quiroga2018-05-037-9/+9
| | | | | | It can do 32-bit packing too now. Reviewed-by: Jason Ekstrand <[email protected]>
* nir/lower_64bit_packing: extend the pass to handle packing from / to 16-bit.Iago Toral Quiroga2018-05-031-5/+59
| | | | | | | With 16-bit support we can now do 32-bit packing, a follow-up patch will rename the pass to something more generic. Reviewed-by: Jason Ekstrand <[email protected]>
* nir: add opcodes for 16-bit packing and unpackingIago Toral Quiroga2018-05-031-0/+19
| | | | | | | | | | Noitice that we don't need 'split' versions of the 64-bit to / from 16-bit opcodes which we require during pack lowering to implement these operations. This is because these operations can be expressed as a collection of 32-bit from / to 16-bit and 64-bit to / from 32-bit operations, so we don't need new opcodes specifically for them. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: fix 16-bit comparisonsIago Toral Quiroga2018-05-031-8/+30
| | | | | | | | | | | | | | NIR assumes that booleans are always 32-bit, but Intel hardware produces 16-bit booleans for 16-bit comparisons. This means that we need to convert the 16-bit result to 32-bit. In the future we want to add an optimization pass to clean this up and hopefully remove the conversions. v2 (Jason): use the type of the source for the temporary and use brw_reg_type_from_bit_size for the conversion to 32-bit. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: lower some 16-bit integer operations to 32-bitIago Toral Quiroga2018-05-031-0/+21
| | | | | | | | | These are not supported in hardware for 16-bit integers. We do the lowering pass after the optimization loop to ensure that we lower ALU operations injected by algebraic optimizations too. Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/nir: add a lowering pass to convert the bit size of ALU operationsIago Toral Quiroga2018-05-034-0/+134
| | | | | | | | | | | | | | | | Not all bit-sizes may be supported natively in hardware for all operations. This pass allows drivers to lower such operations to a bit-size that is actually supported and then converts the result back to the original bit-size. Compiler backends control which operations and wich bit-sizes require the lowering through a callback function. v2: generalize this pass and make it available in NIR core (Rob, Jason) v3: remove some temporaries and reduce nesting in instruction loop using a continue statement (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: support negate and abs of half float immediatesJose Maria Casanova Crespo2018-05-031-2/+4
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: fix brw_imm_w for negative 16-bit integersJose Maria Casanova Crespo2018-05-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | 16-bit immediates need to replicate the 16-bit immediate value in both words of the 32-bit value. This needs to be careful to avoid sign-extension, which the previous implementation was not handling properly. For example, with the previous implementation, storing the value -3 would generate imm.d = 0xfffffffd due to signed integer sign extension, which is not correct. Instead, we should cast to uint16_t, which gives us the correct result: imm.ud = 0xfffdfffd. We only had a couple of cases hitting this path in the driver until now, one with value -1, which would work since all bits are one in this case, and another with value -2 in brw_clip_tri(), which would hit the aforementioned issue (this case only affects gen4 although we are not aware of whether this was causing an actual bug somewhere). v2: Make explicit uint32_t casting for left shift (Jason Ekstrand) Reviewed-by: Jason Ekstrand <[email protected]> Cc: "18.0 18.1" <[email protected]>
* intel/compiler: fix 16-bit int brw_negate_immediate and brw_abs_immediateJose Maria Casanova Crespo2018-05-031-4/+8
| | | | | | | | | | | | | | | | | | | | | From Intel Skylake PRM, vol 07, "Immediate" section (page 768): "For a word, unsigned word, or half-float immediate data, software must replicate the same 16-bit immediate value to both the lower word and the high word of the 32-bit immediate field in a GEN instruction." This fixes the int16/uint16 negate and abs immediates that weren't taking into account the replication in lower and upper words. v2: Integer cases are different to Float cases. (Jason Ekstrand) Included reference to PRM (Jose Maria Casanova) v3: Make explicit uint32_t casting for left shift (Jason Ekstrand) Split half float implementation. (Jason Ekstrand) Fix brw_abs_immediate (Jose Maria Casanova) Cc: "18.0 18.1" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: implement nir_instr_type_load_const for 16-bit constantsJose Maria Casanova Crespo2018-05-031-0/+5
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: implement conversions from 16-bit int/float to boolIago Toral Quiroga2018-05-031-5/+11
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: implement conversion between float/int 16-bit typesIago Toral Quiroga2018-05-031-0/+4
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compiler: handle conversion to smaller type in the lowering pass for thatIago Toral Quiroga2018-05-032-12/+7
| | | | | | | The lowering pass was specialized to act on 64-bit to 32-bit conversions only, but the implementation is valid for other cases. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: fix isign for 16-bit integersIago Toral Quiroga2018-05-031-5/+12
| | | | | | | | | | | | | We need to use 16-bit constants with 16-bit instructions, otherwise we get the following validation error: "Destination stride must be equal to the ratio of the sizes of the execution data type to the destination type" Because the execution data type is 4B due to the 32-bit integer constant. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Always try to create a logical contextChris Wilson2018-05-031-15/+14
| | | | | | | | | | | | | | | | | Always enable use of HW logical contexts to preserve GPU state between batches when the kernel supports such constructs, continuing to enforce the required support for gen6+. At runtime, this effectively removes the BRW_NEW_CONTEXT flag (and the upload of invariant state) from the start of every batch for any kernel supporting contexts. So long as the older atoms are correctly listening to the right flag (NEW_CONTEXT rather than NEW_BATCH) this should eliminate a few redundant state uploads for the older platforms. No piglits were harmed on ctg and ilk, both with and without logical contexts. Reviewed-by: Kenneth Graunke <[email protected]>
* spirv: Apply OriginUpperLeft to FragCoordNeil Roberts2018-05-031-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This behaviour was changed in 1e5b09f42f694687ac. The commit message for that says it is just a “tidy up” so my assumption is that the behaviour change was a mistake. It’s a little hard to decipher looking at the diff, but the previous code before that patch was: if (builtin == SpvBuiltInFragCoord || builtin == SpvBuiltInSamplePosition) nir_var->data.origin_upper_left = b->origin_upper_left; if (builtin == SpvBuiltInFragCoord) nir_var->data.pixel_center_integer = b->pixel_center_integer; After the patch the code was: case SpvBuiltInSamplePosition: nir_var->data.origin_upper_left = b->origin_upper_left; /* fallthrough */ case SpvBuiltInFragCoord: nir_var->data.pixel_center_integer = b->pixel_center_integer; break; Before the patch origin_upper_left affected both builtins and pixel_center_integer only affected FragCoord. After the patch origin_upper_left only affects SamplePosition and pixel_center_integer affects both variables. This patch tries to restore the previous behaviour by changing the code to: case SpvBuiltInFragCoord: nir_var->data.pixel_center_integer = b->pixel_center_integer; /* fallthrough */ case SpvBuiltInSamplePosition: nir_var->data.origin_upper_left = b->origin_upper_left; break; This change will be important for ARB_gl_spirv which is meant to support OriginLowerLeft. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Fixes: 1e5b09f42f694687ac "spirv: Tidy some repeated if checks..."
* spirv: convert some operands for bitwise shift and bitwise ops to uint32Samuel Iglesias Gonsálvez2018-05-031-0/+35
| | | | | | | | | | | | | | | | | SPIR-V allows to define the shift, offset and count operands for shift and bitfield opcodes with a bit-size different than 32 bits, but in NIR the opcodes have that limitation. As agreed in the mailing list, this patch adds a conversion to 32 bits to fix this. For more info, see: https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html v2: - src_bit_size will have zero value for variable bit-size operands (Jason). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: enable geom shaders in OpenGL 3.2 Compat profileTimothy Arceri2018-05-031-2/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radv: UseEnumerateInstanceVersion for the default version.Bas Nieuwenhuizen2018-05-021-1/+1
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Don't check the incoming apiVersion on CreateInstance.Bas Nieuwenhuizen2018-05-021-9/+0
| | | | | | | | | This fixes dEQP-VK.api.device_init.create_instance_invalid_api_version CC: 18.1 <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Allow vkEnumerateInstanceVersion ProcAddr without instance.Bas Nieuwenhuizen2018-05-021-1/+1
| | | | | | | | | | | | Apparently the somewhere between 1.1.70 and 1.1.73 the loader started depending on this. The loader then creates a 1.0 instance, which gets into funny situation because we have a 1.1 device. No idea how to do line wrapping in Mako though, my random guesses did not work. CC: 18.1 <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
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