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* docs: Update release calendar, add news item, and add release notes for 18.1.5Dylan Baker2018-07-273-7/+8
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* docs: Add sha-256 sums for 18.1.5Dylan Baker2018-07-271-2/+2
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* docs: add 18.1.5 release notesDylan Baker2018-07-271-0/+183
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* intel/compiler: fix lower conversions to account for predicationIago Toral Quiroga2018-07-271-1/+4
| | | | | | | | The pass can create a temporary result for the instruction and then moves from it to the original destination, however, if the original instruction was predicated, the mov has to be predicated as well. Reviewed-by: Jose Maria Casanova Crespo <[email protected]>
* radv: allocate enough space in radv_cmd_buffer_after_draw()Samuel Pitoiset2018-07-271-0/+2
| | | | | | | | The driver might emit up to 4 dwords when RADV_TRACE_FILE is used. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: check CS space in radv_emit_write_data_packet()Samuel Pitoiset2018-07-271-14/+12
| | | | | | | | This wasn't wrong but it looks better to me like this. It's only used for debugging purposes (ie. RADV_TRACE_FILE). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not emit pipeline stats flushes on compute queueSamuel Pitoiset2018-07-271-1/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: reduce CB/DB meta flushes in radv_dst_access_flush()Samuel Pitoiset2018-07-271-8/+23
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Fix buildKenneth Graunke2018-07-261-1/+1
| | | | | | I renamed this pass and forgot to update radv. Fixes: 488972222c6454551ab1559f753c13a493dc513f ("i965: Combine both gl_PatchVerticesIn lowering passes.")
* i965: Combine both gl_PatchVerticesIn lowering passes.Kenneth Graunke2018-07-266-62/+84
| | | | | | | | | | | | | | | | | | Until now, we had separate passes for lowering gl_PatchVerticesIn to a statically known constant (for TES inputs when linked against a TCS), and a uniform in the other cases. Annoyingly, one had to be run before nir_lower_system_values, and the other afterward. This simplified the passes, but made life painful for the callers. This patch combines both into a single pass. If you give it a non-zero static count, it uses that. If you give it Mesa state slots, it turns it back into a built-in uniform. Otherwise, it does nothing. This also moves the i965 uniform lowering out to shared code. v2: Make token arrays const. Reviewed-by: Eric Anholt <[email protected]>
* i965: Expose EXT_base_instance extension in OpenGLES 3.0Sagar Ghuge2018-07-261-1/+1
| | | | | | | | | | | | | | The extension requires at least OpenGL 3.0 and OpenGL ES 3.0. Fixes two ext_base_instance tests: arb_base_instance-baseinstance-doesnt-affect-gl-instance-id_gles3 arb_base_instance-drawarrays_gles3 Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* radv: Add support for ETC2 textures.Bas Nieuwenhuizen2018-07-273-11/+49
| | | | | | Was surprised that is even supported by Vega. Reviewed-by: Samuel Pitoiset <[email protected]>
* clover: Reduce wait_count in abort path.Jan Vesely2018-07-261-1/+3
| | | | | | | | | | Trigger waiter condition variable. Passes 'events' CTS on carrizo and turks. v2: reduce to 0 Cc: [email protected] Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* clover: Don't extend illegal integer types.Jan Vesely2018-07-262-2/+13
| | | | | | | | | | | | | | | | | It's OK to pass them in memory, which is what kernel invocation needs. Fixes regressions since llvm r337535 ("Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering"): scalar-arithmetic-char scalar-arithmetic-uchar scalar-arithemtic-short scalar-arithmetic-ushort scalar-comparison-char scalar-comparison-uchar scalar-comparison-short scalar-comparison-ushort Cc: [email protected] Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* intel/compiler: Delete dead VS intrinsic handling.Kenneth Graunke2018-07-261-12/+4
| | | | | | | These are lowered by brw_nir_lower_vs_inputs(). If they weren't, we would have already hit the unreachable() in emit_system_values_block(). Reviewed-by: Jason Ekstrand <[email protected]>
* v3d: Avoid the GFXH-1461 workaround if we have only Z or only S.Eric Anholt2018-07-261-4/+6
| | | | | | This seems like a sensible precaution to avoid extra draws. It doesn't deal with the case of a Z24S8 buffer created by the window system for an application that happens to never use S.
* v3d: Rework the ordering of how we clear things.Eric Anholt2018-07-261-31/+54
| | | | | | | | | First, figure out if we can just sneak the clear into the TLB clear, even if drawing has already happened (since we have job->load and job->clear to tell us), taking into account GFXH-1461. For any pieces we can't TLB clear, fall back to drawing a quad without flushing the scene. Fixes extra scene flushes in glmark2 due to GFXH-1461.
* v3d: Only store buffers that have been written to.Eric Anholt2018-07-261-3/+9
| | | | | I've seen cases where a color buffer is bound, but only Z is written, and we end up storing color.
* v3d: Track the buffers being loaded separately.Eric Anholt2018-07-263-1/+8
| | | | | | We were computing this at RCL generation time, but that means you can't unflag the store for an invalidate_resource, or not flag the store if writmasking is disabled.
* v3d: Rename cleared/resolve to clear/store.Eric Anholt2018-07-265-35/+35
| | | | | | These describe what the fields mean in RCL generation. "resolve" is left over from VC4, and sounds like MSAA resolves (which may or may not be involved in the store we generate).
* nir: Add flipping of gl_PointCoord.y in nir_lower_wpos_ytransform.Eric Anholt2018-07-263-0/+33
| | | | | | | This is controlled by a new nir_shader_compiler_options flag, and fixes dEQP-GLES3.functional.shaders.builtin_variable.pointcoord on V3D. Reviewed-by: Kenneth Graunke <[email protected]>
* docs: fix incorrect placement of the ARB_sample_locations release notesRhys Perry2018-07-261-4/+1
| | | | | | | | | Seems something went wrong somehow when it was pushed. v2: combine into one list Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Marek OIšák <[email protected]>
* anv: drop unused local varsEric Engestrom2018-07-261-6/+0
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: remove incorrect `UNUSED` flagEric Engestrom2018-07-261-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* gallium: initialize ureg_dst::Invariant bitErik Faye-Lund2018-07-261-0/+3
| | | | | | | | | | | | | | | | | | | | | When this bit was added, it seems the some initialization code was omitted by mistake. Since stack-variables have kinda random contents, and we don't zero initialize the whole struct in these code-paths, we end up getting random-ish values for this bit. Spotted by Coverity in the following CIDs: - 1438115 - 1438123 - 1438130 Fixes: 70425bcfe63c4e9191809659d019ec4af923595d ("gallium: plumb invariant output attrib thru TGSI") Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* radv: fix adjusting vertex fetches since 16bit supportSamuel Pitoiset2018-07-261-3/+4
| | | | | | | | | | | Move the integer conversion after the fixup. This fixes some regressions with dEQP-VK.pipeline.vertex_input.single_attribute.mat4.as_a2r10g10b10* Fixes: b722b29f10 ("radv: add support for 16bit input/output") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir: remove wrong assertion in print_var_decl()Samuel Pitoiset2018-07-261-1/+0
| | | | | | | | | This breaks printing input/output variables with more than 4 components like mat4. Fixes: 1beef89ad8 ("nir: prepare for bumping up max components to 16") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: fix typo DSL_SEL -> DST_SELMarek Olšák2018-07-263-6/+6
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* radeonsi: update a comment about cache behaviorMarek Olšák2018-07-261-3/+3
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* intel: Make the decoder just store addresses for bases, not buffers.Kenneth Graunke2018-07-252-12/+12
| | | | | | | | | | The various base addresses are simply addresses. There may or may not be a buffer located at those addresses. So, it doesn't make much sense to request one. Just save the raw address so we can add it later, when asking about BOs at the final <base + offset> address. Suggested-by: Lionel Landwerlin <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: Make the decoder handle STATE_BASE_ADDRESS not being a buffer.Kenneth Graunke2018-07-252-38/+46
| | | | | | | | | | | | | | | | | | | | | | | | Normally, i965 programs STATE_BASE_ADDRESS every batch, and puts all state for a given base in a single buffer. I'm working on a prototype which emits STATE_BASE_ADDRESS only once at startup, where each base address is a fixed 4GB region of the PPGTT. State may live in many buffers in that 4GB region, even if there isn't a buffer located at the actual base address itself. To handle this, we need to save the STATE_BASE_ADDRESS values across multiple batches, rather than assuming we'll see the command each time. Then, each time we see a pointer, we need to ask the driver for the BO map for that data. (We can't just use the map for the base address, as state may be in multiple buffers, and there may not even be a buffer at the base address to map.) v2: Fix things caught in review by Lionel: - Drop bogus bind_bo.size check. - Drop "get the BOs again" code - we just get the BOs as needed - Add a message about interface descriptor data being unavailable Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: don't crash on vkDestroyDevice(NULL)Eric Engestrom2018-07-251-1/+3
| | | | | | | | CovID: 1438132 Fixes: a99c9e63a07477634ab73 "anv: finish the binding_table_pool on destroyDevice when use_softpin" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jose Maria Casanova Crespo <[email protected]>
* vulkan/wsi: fix incorrect assignment in assert()Eric Engestrom2018-07-251-2/+2
| | | | | | | CovID: 1438113, 1438118, 1438119, 1438121 Fixes: dc1d10b396179766227df "anv,radv: Add support for VK_KHR_get_display_properties2" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: fix python whitespace warningEric Engestrom2018-07-251-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* anv: cleanup python importsEric Engestrom2018-07-252-3/+3
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* anv: remove unnecessary semicolons in pythonEric Engestrom2018-07-251-3/+3
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* st/nir: Fix st_nir_opts() prototype.Kenneth Graunke2018-07-251-1/+1
| | | | | | | | | | | | This wasn't updated for the new scalar ISA parameter. It worked anyway because all the function's callers live in the same file, so it found the correct function. Tim made this external for the new st prog_to_nir translator, which got reverted, but which I'd like to land eventually. So, fix the prototype. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* intel: tools: dump: only store device id on successLionel Landwerlin2018-07-251-2/+2
| | | | | | | | We might fail on master node drm fd because we won't have the right permissions. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* r600: Scale integer valued texture border colors to float (v2)Gert Wollny2018-07-251-1/+44
| | | | | | | | | | | | | | | | | | | | | | | | It seems the hardware always expects floating point border color values [0,1] for unsigned, and [-1,1] for signed texture component, regardless of pixel type, but the border colors are passed according to texture component type. Hence, before submitting the border color, convert and scale it these ranges accordingly. This doesn't seem to work for textures with 32 bit integer components though, here, it seems that the border color is always set to zero, regardless of the BORDER_COLOR_TYPE state set in Q_TEX_SAMPLER_WORD0_0. v2: Simplyfy logic as suggested by Roland Schneidegger Fixes: dEQP-GLES31.functional.texture.border_clamp.formats.compressed* dEQP-GLES31.functional.texture.border_clamp.formats.r* (non 32 bit integer) dEQP-GLES31.functional.texture.border_clamp.per_axis_wrap_mode.texture_2d* and a number of piglits out of piglit run gpu -t texture -t gather -t formats Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* nir: Add a couple of iand/ior optimizationsJason Ekstrand2018-07-241-0/+4
| | | | | | Spotted in a shader in Batman: Arkham City. Reviewed-by: Timothy Arceri <[email protected]>
* i965, anv: Use INTEL_DEBUG for disk_cache driver flagsJordan Justen2018-07-243-2/+9
| | | | | | | | | | | | | | | | | | | Since various options within INTEL_DEBUG could impact code generation, we need to set the disk cache driver_flags parameter based on the INTEL_DEBUG flags in use. An example that will affect the program generated by i965 is the INTEL_DEBUG=nocompact option. The DEBUG_DISK_CACHE_MASK value is added to mask the settings of INTEL_DEBUG that can affect program generation. v2: * Use driver_flags (Tim) * Also update Anvil (Jason) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965, anv: Add extra unused character in disk_cache renderer temp stringJordan Justen2018-07-242-4/+5
| | | | | | | | | | | | This extra character should not be used by snprintf, but we make it available to verify that we printed the exact number we wanted, and didn't overflow. v2: * Also update Anvil Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* mesa: allow indirect draws with the default VAO and compatibility profileMarek Olšák2018-07-241-1/+2
| | | | Reviewed-by: Eric Anholt <[email protected]>
* mesa: Fix copy-paste error in ConservativeRasterDilateRange initializationDanylo Piliaiev2018-07-241-1/+1
| | | | | | | | Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Fixes: 4580617509d ("mesa: add support for nvidia conservative rasterization extensions") Reviewed-by: Emil Velikov <[email protected]>
* nir/serialize: Alloc constants off the variableJason Ekstrand2018-07-241-1/+1
| | | | | | | | | | | nir_sweep assumes that constants area always allocated off the variable to which they belong. Violating this assumption causes them to get freed early and leads to use-after-free bugs. Fixes: 120da00975541 "nir: add serialization and deserialization" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107366 Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Mark Janes <[email protected]>
* nir: rename f2f16_undef to f2f16Karol Herbst2018-07-245-11/+11
| | | | | | | | | | | we need rounding modes on other conversions involving floats and it is easier to rename f2f16_undef than renaming all the other ones. v2: rebased on master Reviewed-by: Jason Ekstrand <[email protected]> Acked-by: Rob Clark <[email protected]> Signed-off-by: Karol Herbst <[email protected]>
* nir: add builtin builderKarol Herbst2018-07-245-45/+166
| | | | | | | | | | | also move some of the GLSL builtins over we will need for implementing some OpenCL builtins v2: replace NIR_IMM_FP by nir_imm_floatN_t in ported code fix up changes caused by swizzle rework Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Karol Herbst <[email protected]>
* nir/spirv: import OpenCL.std.hRob Clark2018-07-241-0/+211
| | | | | | | | | Lightly edited to be valid 'C' code. Is there a bug open to fix this upstream? Acked-by: Jason Ekstrand <[email protected]> Signed-off-by: Karol Herbst <[email protected]>
* radeonsi: handle SI_FORCE_FAMILY earlyMarek Olšák2018-07-241-2/+1
| | | | before LLVM target machines are created
* python: Use range() instead of xrange()Mathieu Bridon2018-07-249-12/+12
| | | | | | | | | | | | | | | | Python 2 has a range() function which returns a list, and an xrange() one which returns an iterator. Python 3 lost the function returning a list, and renamed the function returning an iterator as range(). As a result, using range() makes the scripts compatible with both Python versions 2 and 3. Signed-off-by: Mathieu Bridon <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
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