| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | radeonsi: Fix memory leaks if returning early from some state functions. | Michel Dänzer | 2012-08-16 | 2 | -12/+14 |
| | | | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]> | ||||
| * | radeonsi: Fix LLVM context leak. | Michel Dänzer | 2012-08-16 | 1 | -0/+1 |
| | | | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]> | ||||
| * | gallium/radeon: Don't assign virtual address space for BO that already has one. | Michel Dänzer | 2012-08-16 | 1 | -1/+1 |
| | | | | | | | | | We'd end up re-using the old one and throwing away the new one anyway, but only after a roundtrip to the kernel. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]> | ||||
| * | gallium/radeon: Create hole for waste when allocating from va_offset. | Michel Dänzer | 2012-08-16 | 1 | -0/+6 |
| | | | | | | | | Otherwise, the wasted area could never be used for an allocation again. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]> | ||||
| * | gallium/radeon: Fix potential address space loss in radeon_bomgr_force_va(). | Michel Dänzer | 2012-08-16 | 1 | -6/+13 |
| | | | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]> | ||||
| * | gallium/radeon: Delete uppermost virtual address space hole if it's at the top. | Michel Dänzer | 2012-08-16 | 1 | -1/+12 |
| | | | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]> | ||||
| * | gallium/radeon: Fix losing holes when allocating virtual address space. | Michel Dänzer | 2012-08-16 | 1 | -1/+6 |
| | | | | | | | | | | If a hole exactly matches the allocated size plus alignment, we would fail to preserve the alignment as a hole. This would result in never being able to use the alignment area for an allocation again. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]> | ||||
| * | gallium/radeon: Merge holes when freeing virtual address space. | Michel Dänzer | 2012-08-16 | 1 | -7/+38 |
| | | | | | | | | | | | Otherwise we'll likely end up with an ever increasing amount of ever smaller holes. Requires keeping the list ordered wrt offsets. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]> | ||||
| * | gallium/radeon: Make va_offset 64 bits wide. | Michel Dänzer | 2012-08-16 | 1 | -1/+1 |
| | | | | | | | | | | | Otherwise we'd wrap around after 32 bits. The kernel currently limits GPU virtual address space to 4GB anyway, but that will probably change sooner or later, and this would result in confusing error messages when running out of virtual address space even now. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]> | ||||
| * | llvmpipe: Silence Coverity incorrect sizeof expression defect. | Vinson Lee | 2012-08-15 | 1 | -1/+1 |
| | | | | | | Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: José Fonseca <[email protected]> | ||||
| * | scons: Add option to enable floating-point textures. | Vinson Lee | 2012-08-15 | 2 | -0/+5 |
| | | | | | | Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: José Fonseca <[email protected]> | ||||
| * | glx/dri2: add dri2 prime support. | Dave Airlie | 2012-08-16 | 1 | -0/+13 |
| | | | | | | | | | | | This adds support for having libGL pick a different driver for prime support. DRI_PRIME env var is set to the value retrieved from the server randr provider calls, by the calling process. (generally DRI_PRIME=1 will be the right answer). Signed-off-by: Dave Airlie <[email protected]> | ||||
| * | radeon/llvm: Enable if-cvt | Vincent Lejeune | 2012-08-15 | 1 | -0/+3 |
| | | | | | Signed-off-by: Tom Stellard <[email protected]> | ||||
| * | radeon/llvm: Add callbacks needed by if-cvt | Vincent Lejeune | 2012-08-15 | 2 | -2/+151 |
| | | | | | Signed-off-by: Tom Stellard <[email protected]> | ||||
| * | radeon/llvm: Lower branch/branch_cond into predicated jump | Vincent Lejeune | 2012-08-15 | 7 | -145/+278 |
| | | | | | Signed-off-by: Tom Stellard <[email protected]> | ||||
| * | radeon/llvm: Add a predicated JUMP instruction | Vincent Lejeune | 2012-08-15 | 1 | -0/+9 |
| | | | | | Signed-off-by: Tom Stellard <[email protected]> | ||||
| * | radeon/llvm: Support for predicate bit | Vincent Lejeune | 2012-08-15 | 8 | -13/+125 |
| | | | | | | | | Tom Stellard: - A few changes to predicate register defs Signed-off-by: Tom Stellard <[email protected]> | ||||
| * | r600g: Glue to handle predicate aware output from llvm | Vincent Lejeune | 2012-08-15 | 1 | -11/+22 |
| | | | | | Signed-off-by: Tom Stellard <[email protected]> | ||||
| * | r600g: Fix instruction group merge when there are predicated insts. | Vincent Lejeune | 2012-08-15 | 1 | -0/+18 |
| | | | | | Signed-off-by: Tom Stellard <[email protected]> | ||||
| * | radeon/llvm: Do not use PV/PS if PRED_SEL does not match | Vincent Lejeune | 2012-08-15 | 1 | -2/+4 |
| | | | | | Signed-off-by: Tom Stellard <[email protected]> | ||||
| * | r600g: Add support for predicates | Vincent Lejeune | 2012-08-15 | 4 | -11/+18 |
| | | | | | Signed-off-by: Tom Stellard <[email protected]> | ||||
| * | radeonsi: move ps sampler state into PM4 stream | Christian König | 2012-08-15 | 1 | -17/+7 |
| | | | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> | ||||
| * | radeonsi: move ps sampler views into PM4 stream | Christian König | 2012-08-15 | 1 | -22/+7 |
| | | | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> | ||||
| * | radeonsi: move vertex state descriptors into PM4 stream | Christian König | 2012-08-15 | 1 | -27/+9 |
| | | | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> | ||||
| * | radeonsi: add shader data infrastructure | Christian König | 2012-08-15 | 3 | -2/+40 |
| | | | | | | | | | With this we can embed data for the shaders (like resource descriptors) into the PM4 stream. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> | ||||
| * | radeon/llvm: add support to fetch temps as vectors | Christian König | 2012-08-15 | 1 | -1/+11 |
| | | | | | | | | | Necessary for texture fetches with temp regs as source on SI. Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Alex Deucher <[email protected]> | ||||
| * | radeon/llvm: Remove AMDGPUUtil.cpp | Tom Stellard | 2012-08-15 | 8 | -81/+22 |
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| * | radeon/llvm: Cleanup AMDGPUUtil.cpp | Apostolos Bartziokas | 2012-08-15 | 6 | -119/+95 |
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| * | radeon/llvm: Lower loads from USE_SGPR adddress space during DAG lowering | Tom Stellard | 2012-08-15 | 5 | -66/+50 |
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| * | radeon/llvm: Add live-in registers during DAG lowering | Tom Stellard | 2012-08-15 | 9 | -66/+82 |
| | | | | | | | Psuedo instructions emulating live-in registers have been removed and their corresponding intrinsics are now being lowered during DAG lowering. | ||||
| * | radeon/llvm: Lower store_output intrinsic during DAG lowering | Tom Stellard | 2012-08-15 | 3 | -22/+22 |
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| * | radeon/llvm: Force VTX_READ instructions to use same reg for src and dst | Tom Stellard | 2012-08-15 | 1 | -0/+14 |
| | | | | | | | I was seeing some GPU hangs that seemed to be cause by ALU instructions writing to the same register used as the source for VTX_READ. Adding this constraint to the VTX_READ instructions avoids this situation. | ||||
| * | radeonsi: fix build breakage after u_blitter changes | Marek Olšák | 2012-08-15 | 1 | -3/+3 |
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| * | gallium/u_blitter: document custom meta helpers | Marek Olšák | 2012-08-15 | 4 | -10/+19 |
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| * | r600g: disable handling of DISCARD_RANGE | Marek Olšák | 2012-08-15 | 1 | -0/+2 |
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=53130 | ||||
| * | r600g: implement timestamp query and get_timestamp hook | Marek Olšák | 2012-08-15 | 4 | -2/+56 |
| | | | | | Reviewed-by: Alex Deucher <[email protected]> | ||||
| * | r600g: enable MSAA on evergreen by default | Marek Olšák | 2012-08-15 | 1 | -3/+24 |
| | | | | | v2: add the DRM version check | ||||
| * | r600g: implement copying between MSAA textures | Marek Olšák | 2012-08-15 | 1 | -4/+10 |
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| * | r600g: implement MSAA color resolve | Marek Olšák | 2012-08-15 | 6 | -3/+177 |
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| * | r600g: implement MSAA depth-stencil decompression and resolve | Marek Olšák | 2012-08-15 | 6 | -35/+143 |
| | | | | | and integer textures, which are resolved the same as depth, I think. | ||||
| * | r600g: implement TXQ_LZ opcode | Marek Olšák | 2012-08-15 | 1 | -7/+15 |
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| * | r600g: implement MSAA rendering and texturing for evergreen and cayman | Marek Olšák | 2012-08-15 | 4 | -26/+232 |
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| * | r600g: implement set_sample_mask | Marek Olšák | 2012-08-15 | 6 | -17/+61 |
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| * | r600g: implement alpha-to-coverage | Marek Olšák | 2012-08-15 | 6 | -6/+32 |
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| * | r600g: implement alpha-to-one | Marek Olšák | 2012-08-15 | 5 | -2/+20 |
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| * | r600g: remove support for 3-channel colorbuffers | Marek Olšák | 2012-08-15 | 2 | -15/+0 |
| | | | | | We have no sampler support for them. | ||||
| * | configure.ac: bump libdrm_radeon requirement to 2.6.38 | Marek Olšák | 2012-08-15 | 2 | -2/+1 |
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| * | winsys/radeon: print error if CS is overflowed | Marek Olšák | 2012-08-15 | 1 | -2/+6 |
| | | | | | and don't submit the CS to the kernel. | ||||
| * | gallium/u_blitter: implement X and Y texture flipping | Marek Olšák | 2012-08-15 | 1 | -11/+26 |
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| * | gallium/u_blitter: implement blitting multisample resources | Marek Olšák | 2012-08-15 | 9 | -105/+348 |
| | | | | | It can blit only one sample at a time (it should be called in a loop). | ||||
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