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* nvc0/ir: fix texture barrier insertion to prevent WAW hazardsChristoph Bumiller2012-05-296-29/+88
| | | | Fixes, for instance, object highlighting in Diablo 3 (wine).
* nvc0/ir: TEX doesn't support JOIN modifier eitherChristoph Bumiller2012-05-291-0/+1
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* gallium: add st_api feature mask to prevent advertising MS visualsChristoph Bumiller2012-05-294-12/+37
| | | | | | | | | | | | | | v2: use a define for the maximum sample count v3: also test odd sample counts (r300 supports MS3) While multisample renderbuffers are supported by mesa, MS visuals are not, so we need a way to tell dri/st not to advertise them even if the gallium driver does support multisampled surfaces. Otherwise applications selecting these non-functional visuals would run into trouble ... Reviewed-by: Brian Paul <[email protected]>
* nv30: Fix generic passing to fragment program in NV34.Roy Spliet2012-05-253-5/+9
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* nv30: handle user index buffersChristoph Bumiller2012-05-254-17/+27
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* radeon/llvm: Use a custom inserter for MASK_WRITETom Stellard2012-05-254-34/+36
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* radeon/llvm: Use tablegen pattern to lower bitconvertTom Stellard2012-05-254-294/+11
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* radeon/llvm: Use a custom inserter to lower FNEGTom Stellard2012-05-255-22/+15
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* radeon/llvm: Use a custom inserter to lower CLAMPTom Stellard2012-05-259-84/+41
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* radeon/llvm: Use a custom inserter to lower FABSTom Stellard2012-05-2510-42/+41
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* r600g: handle R16G16B16_FLOAT and R32G32B32_FLOAT in translate_colorswapKai Wasserbäch2012-05-251-0/+2
| | | | | | Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50318 Signed-off-by: Kai Wasserbäch <[email protected]>
* draw: fix primitive restart bug by using the index buffer offsetBrian Paul2012-05-251-3/+6
| | | | | | | | | | | The code which scans the index buffer for restart indexes wasn't adding the index buffer offset so we were always starting at offset=0. The offset is usually zero so it wasn't noticed before. Fixes a failure in the piglit primitive-restart test when testing vertex data + index data in a single VBO. NOTE: This is a candidate for the 8.0 branch.
* svga: remove the special zero-stride vertex array codeBrian Paul2012-05-259-153/+12
| | | | | This code actually hasn't been needed for some time now. We can just treat a zero-stride vertex array like any other non-zero-stride array.
* gallium/docs: beef up the docs related to color clampingBrian Paul2012-05-252-3/+18
| | | | Reviewed-by: Marek Olšák <[email protected]>
* util: add GALLIUM_LOG_FILE option for logging output to a fileBrian Paul2012-05-252-6/+25
| | | | Useful for logging different runs to files and diffing, etc.
* i965/msaa: Enable 4x MSAA on Gen7.Paul Berry2012-05-252-9/+9
| | | | | | | | | | | | | | | | | | Basic 4x MSAA support now works on Gen7. This patch enables it. As with Gen6, MSAA support is still fairly preliminary. In particular, the following are not yet supported: - 8x oversampling (Gen7 has hardware support for this, but we do not yet expose it). - Fully general blits between MSAA and non-MSAA buffers. - Formats other than RGBA8, DEPTH24, and STENCIL8. - Centrold interpolation. - Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE, GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE, GL_SAMPLE_COVERAGE_INVERT). Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Implement manual blending operation for Gen7.Paul Berry2012-05-251-23/+67
| | | | | | | | | | | | | | | On Gen6, the blending necessary to blit an MSAA surface to a non-MSAA surface could be accomplished with a single texturing operation. On Gen7, the WM program must fetch each sample and blend them together manually. From the Bspec (Shared Functions/Messages/Initiating Message/Message Types/sample): [DevIVB+]:Number of Multisamples on the associated surface must be MULTISAMPLECOUNT_1. This patch implements the manual blend operation. Acked-by: Kenneth Graunke <[email protected]>
* i965/msaa: Modify blorp code to account for Gen7 MSAA layouts.Paul Berry2012-05-253-68/+151
| | | | | | | | | | | | | | | | | | | Since blorp uses color textures and render targets to do all its work (even when blitting stencil and depth data), it always has to configure the Gen7 GPU to use the new "sliced" MSAA layout. However, when blitting stencil or depth data, the actual MSAA layout is interleaved (as in Gen6). Therefore, blorp has to do extra coordinate transformation work to account for the interleaving manually. This patch causes blorp to perform the necessary extra coordinate transformations. It also modifies the blorp SURFACE_STATE setup code for Gen7, so that it does not try to correct the surface width and height to account for MSAA, since "sliced" MSAA layout doesn't affect the surface width or height. Acked-by: Kenneth Graunke <[email protected]>
* i965/msaa: Validate Gen7 surface state constraints.Paul Berry2012-05-253-3/+109
| | | | | | | | | When a Gen7 SURFACE_STATE is configured for MSAA, a number of additional constaints come in to play. This patch adds a function gen7_check_surface_setup() which verifies that all of those constraints are met. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Properly handle sliced layout for Gen7.Paul Berry2012-05-2510-58/+162
| | | | | | | | | | | | | | | | | | | | | | | | | Starting in Gen7, there are two possible layouts for MSAA surfaces: - Interleaved, in which additional samples are accommodated by scaling up the width and height of the surface. This is the only layout available in Gen6. On Gen7 it is used for depth and stencil surfaces only. - Sliced, in which the surface is stored as a 2D array, with array slice n containing all pixel data for sample n. On Gen7 this layout is used for color surfaces. The "Sliced" layout has an additional requirement: it must be used in ARYSPC_LOD0 mode, which means that the surface doesn't leave any extra room between array slices for miplevels other than 0. This patch modifies the surface allocation functions to use the correct layout when allocating MSAA surfaces in Gen7, and to set the array offsets properly when using ARYSPC_LOD0 mode. It also modifies the code that populates SURFACE_STATE structures to ensure that ARYSPC_LOD0 mode is selected in the appropriate circumstances. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Add defines for Gen7.Paul Berry2012-05-251-0/+5
| | | | | | Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Enable blorp blits on Gen7.Paul Berry2012-05-252-2/+4
| | | | | | | | | | | | | Gen7 support for blorp (blits using the render bath) now works for non-MSAA purposes. This patch enables it. Since blorp operations re-use the logic for HiZ ops, this required adding a case to the switch statement in gen7_blorp_emit_wm_config(), to allow for the case where no HiZ op is being performed. Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Implement proper texel fetch messages for Gen7.Paul Berry2012-05-252-2/+31
| | | | | | | | | | | | | | | | | On Gen6, texel fetch is always accomplished using the SAMPLE_LD message, which accepts arguments (u, v, r, lod, si). On Gen7, there are two* texel fetch messages: SAMPLE_LD for non-MSAA surfaces, taking arguments (u, lod, v), and SAMPLE_LD2DSS for MSAA surfaces, taking arguments (si, u, v). *Technically, there are other texel fetch messages, but they are used for "compressed" MSAA surfaces, which we don't yet support. This patch adds the proper message types and argument orderings for Gen7. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Use 16 pixel dispatch on Gen7.Paul Berry2012-05-251-1/+9
| | | | | | | | | | | | | | | | | Gen7 hardware requires us to enable at least one WM dispatch mode, even if there is no program being dispatched to. When this code was only used for HiZ operations (which don't use a WM program), we used 32-pixel dispatch, because it didn't matter. But blit programs are compiled for 16-pixel dispatch. So just enable 16-wide dispatch unconditionally. Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> v2: Enable 16-wide dispatch unconditionally rather than add the unnecessary complication of using 32-wide dispatch when there is no WM program.
* i965/blorp: Allocate space for push constants on Gen7.Paul Berry2012-05-253-30/+28
| | | | | | | | | | | | | | | | | | On Gen7, push constants for shader programs are stored in the URB, so blorp code needs to set aside space for them. This was previously unnecessary because blorp code was based on HiZ operations, which don't require any shaders. This patch adds a call from gen7_blorp_exec() to gen7_allocate_push_constants(), to ensure that push constants are assigned the correct location in the URB. It also extracts a new function gen7_emit_urb_state() from gen7_upload_urb(), which is re-used by gen7_blorp_emit_urb_config() to ensure that the URB regions used by all the pipeline stages leave room for the push constants. Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Set the dynamic state upper bound.Paul Berry2012-05-251-1/+6
| | | | | | | | | | | We know from previous bug fixes (commits c25e5300cba7628b58df93ead14ebc3cc32f338c and b2ace06cbbbb1021e2d7ace12a985c6406821939) that texture border color doesn't work if the dynamic state upper bound is set to 0. Although the blorp engine doesn't make use of texture borders, it seems like we ought to err on the safe side and set this value properly. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Factor gen6_blorp_emit_batch_head into separate functions.Paul Berry2012-05-253-34/+49
| | | | | | | | | | | | This patch separates out the portions of gen6_blorp_emit_batch_head() that emit 3DSTATE_MULTISAMPLE, 3DSTATE_SAMPLE_MASK, and STATE_BASE_ADDRESS. This paves the way for making the blorp code work on Gen7, where additional command packets (3DSTATE_PUSH_CONSTANT_ALLOC_VS and 3DSTATE_PUSH_CONSTANT_ALLOC_PS) need to be emitted before 3DSTATE_MULTISAMPLE. Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Use MSDISPMODE_PERSAMPLE rendering when necessaryPaul Berry2012-05-254-27/+87
| | | | | | | | | | | | | | This patch modifies the "blorp" WM program so that it can be run in MSDISPMODE_PERSAMPLE (which means that every single sample of a multisampled render target is dispatched to the WM program, not just every pixel). Previously we were using the ugly hack of configuring multisampled destination surfaces as single-sampled, and generating sample indices other than zero by swizzling the pixel coordinates in the WM program. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/blorp: Emit sample index in SAMPLE_LD message when necessaryPaul Berry2012-05-252-21/+36
| | | | | | | | | | | | | This patch modifies the function brw_blorp_blit_program::texel_fetch() to emit the SI (sample index) argument to the SAMPLE_LD message when reading from a sample index other than zero. Previously we were using the ugly hack of configuring multisampled source surfaces as single-sampled, and accessing sample indices other than zero by swizzling the texture coordinates in the WM program. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Generalize sampling code in preparation for Gen7Paul Berry2012-05-251-26/+61
| | | | | | | | | | | | | | | | This patch generalizes the function brw_blorp_blit_program::texture_lookup() so that it prepares the arguments to the sampler message based on a caller-provided array rather than assuming the argument order is always (u, v). This paves the way for the messages we will need to use in Gen7, which use argument orders (u, lod, v) and (si, u, v) (si=sample index). It will also will allow us to read from arbitrary sample indices on Gen6, by supplying the arguments (u, v, r, lod, si) to the SAMPLE_LD message instead of just (u, v). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Expand odd-sized MSAA surfaces to account for interleaving pattern.Paul Berry2012-05-251-5/+40
| | | | | | | | | | | | | | | Gen6 MSAA buffers (and Gen7 MSAA depth/stencil buffers) interleave MSAA samples in a complex pattern that repeats every 2x2 pixel block. Therefore, when allocating an MSAA buffer, we need to make sure to allocate an integer number of 2x2 blocks; if we don't, then some of the samples in the last row and column will be cut off. Fixes piglit tests "EXT_framebuffer_multisample/unaligned-blit {2,4} color msaa" on i965/Gen6. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* gallium/targets: pass ldflags parameter to MKLIBThomas Gstädtner2012-05-251-1/+1
| | | | | | | | | | | Without passing the -ldflags parameter before $(LDFLAGS) in some cases flags will be passed to MKLIB which it does not understand. This might be -m64, -m32 or similar. NOTE: This is a candidate for the 8.0 branch. Signed-off-by: Thomas Gstädtner <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* Revert "r600g: set round_mode to truncate and get rid of tgsi_f2i on evergreen"Vadim Girlin2012-05-252-6/+56
| | | | | | | | | | | | This reverts commit 60bf0f05b472e66bf1175fcec7a274dab6f7e2a3. It seems round_mode behaves differently in some cases depending on the instruction/slot. Reverting it for now. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50232 Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: add FLT_TO_UINT, UINT_TO_FLT instructionsVadim Girlin2012-05-251-0/+20
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: prepare to revert the round mode state to defaultVadim Girlin2012-05-251-2/+9
| | | | | | | Use TRUNC before FLT_TO_INT on evergreen/cayman. Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: fix sampler index in llvm_emit_texVadim Girlin2012-05-251-2/+4
| | | | | | | | | | Sampler index isn't a second source operand for some tgsi texture instructions. Let's assume it's always the last. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50230 Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: fix opcode for RECIP_UINT_r600Vadim Girlin2012-05-251-1/+1
| | | | | | | | Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50312 Signed-off-by: Vadim Girlin <[email protected]> Tested-by: Kai Wasserbäch <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm/loader: convert hardcoded gpu name to optionVadim Girlin2012-05-251-2/+3
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: add RECIP_INT, PRED_SETE_INT to r600_bytecode_get_num_operandsVadim Girlin2012-05-251-0/+2
| | | | | | | | Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50315 Signed-off-by: Vadim Girlin <[email protected]> Tested-by: Kai Wasserbäch <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* i915g: Check for geometry shader earlier in i915_set_constant_buffer.Vinson Lee2012-05-241-4/+4
| | | | | | | Fix resource leak defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* scons: Fix SCons build infrastructure for FreeBSD.Vinson Lee2012-05-244-4/+4
| | | | | | | | This patch gets the FreeBSD SCons build working again. The build still fails though. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeon/llvm: Lower UDIV using the Selection DAGTom Stellard2012-05-248-212/+126
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* radeon/llvm: Remove auto-generated AMDIL->ISA conversion codeTom Stellard2012-05-2414-280/+28
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* radeon/llvm: Remove AMDIL instructions MULHI, SMULTom Stellard2012-05-243-10/+5
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* radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR)Tom Stellard2012-05-248-693/+6
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* radeon/llvm: Remove AMDIL FTOI and ITOF instructionsTom Stellard2012-05-247-316/+7
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* radeon/llvm: Remove AMDIL EXP* instructionsTom Stellard2012-05-245-15/+7
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* radeon/llvm: Remove AMDIL ADD instructionsTom Stellard2012-05-246-179/+4
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* radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT)Tom Stellard2012-05-248-422/+8
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* radeon/llvm: Remove AMDILMachinePeephole passTom Stellard2012-05-244-177/+0
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