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* freedreno/a4xx: texture fixesRob Clark2014-12-096-7/+54
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: cleanup slice alignment/setupRob Clark2014-12-091-36/+14
| | | | | | | | Collapse things back into a setup_slices() which takes the desired alignment as a param. This gets things ready for a4xx which has some slightly different requirements. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-12-096-18/+65
| | | | Signed-off-by: Rob Clark <[email protected]>
* tgsi/lowering: add support to lower TXP (v2)Rob Clark2014-12-092-15/+34
| | | | | | | v2: actually do perspective divide for RECT/SHADOWRECT Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: use build flag to ensure stack is realigned on x86Timothy Arceri2014-12-103-5/+11
| | | | | | | | | | | | | | | | | Nowadays GCC assumes stack pointer is 16-byte aligned even on 32-bits, but that is an assumption OpenGL drivers (or any dynamic library for that matter) can't afford to make as there are many closed- and open- source application binaries out there that only assume 4-byte stack alignment. V4: fix comment and indentation V3: move all sse4.1 build flag config to the same location and add comment as to why we need to do the realign V2: use $target_cpu rather than $host_cpu and setup build flags in config rather than makefile https://bugs.freedesktop.org/show_bug.cgi?id=86788 Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Matt Turner <[email protected]> CC: "10.4" <[email protected]>
* draw: implement TGSI_PROPERTY_VS_WINDOW_SPACE_POSITIONMarek Olšák2014-12-0910-11/+49
| | | | | | | Required by Nine. Tested with util_run_tests. It's added to softpipe, llvmpipe, and r300g/swtcl. Tested-by: David Heidelberg <[email protected]>
* main: return two minor digits for ES shading language versionSamuel Iglesias Gonsalvez2014-12-091-1/+1
| | | | | | | | | | | | | | | For OpenGL ES 3.0 spec, the minor number for SHADING_LANGUAGE_VERSION is always two digits, matching the OpenGL ES Shading Language Specification release number. For example, this query might return the string "3.00". This patch fixes the following dEQP test: dEQP-GLES3.functional.state_query.string.shading_language_version No piglit regression observed. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: invariant qualifier is not valid for shader inputs in GLSL ES 3.00Samuel Iglesias Gonsalvez2014-12-092-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | GLSL ES 3.00 spec, chapter 4.6.1 "The Invariant Qualifier", Only variables output from a shader can be candidates for invariance. This includes user-defined output variables and the built-in output variables. As only outputs can be declared as invariant, an invariant output from one shader stage will still match an input of a subsequent stage without the input being declared as invariant. This patch fixes the following dEQP tests: dEQP-GLES3.functional.shaders.qualification_order.variables.valid.invariant_interp_storage_precision dEQP-GLES3.functional.shaders.qualification_order.variables.valid.invariant_interp_storage dEQP-GLES3.functional.shaders.qualification_order.variables.valid.invariant_storage_precision dEQP-GLES3.functional.shaders.qualification_order.variables.valid.invariant_storage dEQP-GLES3.functional.shaders.qualification_order.variables.invalid.invariant_interp_storage_precision_invariant_input dEQP-GLES3.functional.shaders.qualification_order.variables.invalid.invariant_interp_storage_invariant_input dEQP-GLES3.functional.shaders.qualification_order.variables.invalid.invariant_storage_precision_invariant_input dEQP-GLES3.functional.shaders.qualification_order.variables.invalid.invariant_storage_invariant_input No piglit regressions observed. v2: - Add spec content in the code Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Recompute LegalTypesMask if the GL API has changedIago Toral Quiroga2014-12-092-19/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code computes ctx->Array.LegalTypesMask just once, however, computing this needs to consider ctx->API so we need to make sure that the API for that context has not changed if we intend to reuse the result. The context API can change, at least, if we go through _mesa_meta_begin, since that will always force API_OPENGL_COMPAT until we call _mesa_meta_end. If any operation in between these two calls triggers a call to update_array_format, then we might be caching a value for LegalTypesMask that will not be right once we have called _mesa_meta_end and restored the context API. Fixes the following 179 dEQP tests in i965: dEQP-GLES3.functional.vertex_arrays.single_attribute.strides.fixed.* dEQP-GLES3.functional.vertex_arrays.single_attribute.normalize.fixed.* dEQP-GLES3.functional.vertex_arrays.single_attribute.output_types.fixed.* dEQP-GLES3.functional.vertex_arrays.single_attribute.usages.static_draw.*fixed* dEQP-GLES3.functional.vertex_arrays.single_attribute.usages.stream_draw.*fixed* dEQP-GLES3.functional.vertex_arrays.single_attribute.usages.dynamic_draw.*fixed* dEQP-GLES3.functional.vertex_arrays.single_attribute.usages.static_copy.*fixed* dEQP-GLES3.functional.vertex_arrays.single_attribute.usages.stream_copy.*fixed* dEQP-GLES3.functional.vertex_arrays.single_attribute.usages.dynamic_copy.*fixed* dEQP-GLES3.functional.vertex_arrays.single_attribute.usages.static_read.*fixed* dEQP-GLES3.functional.vertex_arrays.single_attribute.usages.stream_read.*fixed* dEQP-GLES3.functional.vertex_arrays.single_attribute.usages.dynamic_read.*fixed* dEQP-GLES3.functional.vertex_arrays.multiple_attributes.input_types.3_*fixed2* dEQP-GLES3.functional.draw.random.{2,18,28,68,83,106,109,156,181,191} Reviewed-by: Brian Paul <[email protected]>
* mesa: Returns zero samples when querying GL_NUM_SAMPLE_COUNTS when internal ↵Eduardo Lima Mitev2014-12-091-23/+34
| | | | | | | | | | | format is integer From GL ES 3.0 specification, section 6.1.15 Internal Format Queries (page 236), multisampling is not supported for signed and unsigned integer internal formats. Fixes 19 dEQP tests under 'dEQP-GLES3.functional.state_query.internal_format.*'. Reviewed-by: Ian Romanick <[email protected]>
* mesa: Enables GL_RGB and GL_RGBA unsized internal formats for OpenGL ES 3.0Eduardo Lima Mitev2014-12-091-0/+6
| | | | | | | | | | | | GL_RGB and GL_RGBA are valid internal formats on a GLES3 profile. See "Table 1. Unsized Internal Formats" at https://www.khronos.org/opengles/sdk/docs/man3/html/glTexImage2D.xhtml. Fixes 2 dEQP tests: - dEQP-GLES3.functional.state_query.internal_format.rgb_samples - dEQP-GLES3.functional.state_query.internal_format.rgba_samples Reviewed-by: Brian Paul <[email protected]>
* mesa: Considers GL_DEPTH_STENCIL_ATTACHMENT a valid argument for FBO ↵Eduardo Lima Mitev2014-12-091-0/+8
| | | | | | | | | | | | invalidation under GLES3 In OpenGL and OpenGL-ES 3+, GL_DEPTH_STENCIL_ATTACHMENT is a valid attachment point for the family of functions that invalidate a framebuffer object (e.g, glInvalidateFramebuffer, glInvalidateSubFramebuffer, etc). Currently, a GL_INVALID_ENUM error is emitted for this attachment point. Fixes 21 dEQP test failures under 'dEQP-GLES3.functional.fbo.invalidate.*'. Reviewed-by: Ian Romanick <[email protected]>
* vc4: Reserve rb31 instead of r3 for raddr conflict spills.Eric Anholt2014-12-092-11/+45
| | | | | | | | | | This increases the cost of a raddr b conflict spill (save r3 to rb31, move src1 to r3, move rb31 back to r3 when done, instead of just move src1 to r3), but on average thanks to instruction pairing it's more worthwhile to have another accumulator. total instructions in shared programs: 46428 -> 46171 (-0.55%) instructions in affected programs: 38030 -> 37773 (-0.68%)
* vc4: Prioritize allocating accumulators to short-lived values.Eric Anholt2014-12-091-14/+59
| | | | | | | | | | | | | | | | | | The register allocator walks from the end of the nodes array looking for trivially-allocatable things to put on the stack, meaning (assuming everything is trivially colorable and gets put on the stack in a single pass) the low node numbers get allocated first. The things allocated first happen to get the lower-numbered registers, which is to say the fast accumulators that can be paired more easily. When we previously made the nodes match the temporary register numbers, we'd end up putting the shader inputs (VS or FS) in the accumulators, which are often long-lived values. By prioritizing the shortest-lived values for allocation, we can get a lot more instructions that involve accumulators, and thus fewer conflicts for raddr and WS. total instructions in shared programs: 52870 -> 46428 (-12.18%) instructions in affected programs: 52260 -> 45818 (-12.33%)
* r600g: fix regression since UCMP changeDave Airlie2014-12-091-1/+1
| | | | | | | | | | | | Since d8da6deceadf5e48201d848b7061dad17a5b7cac where the state tracker started using UCMP on cayman a number of tests regressed. this seems to be r600g is doing CNDGE_INT for UCMP which is >= 0, we should be doing CNDE_INT with reverse arguments. Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* program: Delete dead _mesa_realloc_instructions.Matt Turner2014-12-082-21/+0
| | | | | | Dead since 2010 (commit 284ce209). Reviewed-by: Ian Romanick <[email protected]>
* swrast: Remove 'inline' from tex filter functions.Matt Turner2014-12-081-26/+26
| | | | | | | | | | Reduces .text size of mesa_dri_drivers.so (i965-only) by 62k, or 1.4%. Note that we don't remove inline from lerp_2d(), which has a comment above it saying it definitely should be inlined. Though, removing the inline keyword from it doesn't actually change the compiled code for me. Reviewed-by: Brian Paul <[email protected]>
* Don't cast the return value of malloc/reallocMatt Turner2014-12-0811-27/+17
| | | | | | | See commit 2b7a972e for the Coccinelle script. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* Use calloc instead of malloc/memset-0Matt Turner2014-12-081-2/+1
| | | | | | | See commit 6bda027e for the Coccinelle script. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* Remove useless checks for NULL before freeingMatt Turner2014-12-0820-72/+39
| | | | | | | See commits 5067506e and b6109de3 for the Coccinelle script. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/skl: Add Skylake PCI IDsKristian Høgsberg2014-12-082-0/+44
| | | | Signed-off-by: Kristian Høgsberg <[email protected]>
* i965/skl: Emit depth stall workaround for gen9 as wellDamien Lespiau2014-12-081-1/+1
| | | | | | | | | | The docs say that we shouldn't need this workaround for gen8+, but just removing it, causes gpu hangs. We'll revisit this, but for now, just extend the workaround to gen9. Signed-off-by: Damien Lespiau <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/skl: Fix GS thread count locationBen Widawsky2014-12-081-11/+18
| | | | | | | | | | SKL moves the GS threadcount to dw8 from dw7, and no longer does the divide by 2 thing. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Tested-by: Kristian Høgsberg <[email protected]>
* i965: Fix union usage for G++ <= 4.6.Vinson Lee2014-12-081-1/+2
| | | | | | | | | | | | This patch fixes this build error with G++ <= 4.6. CXX test_vf_float_conversions.o test_vf_float_conversions.cpp: In function ‘unsigned int f2u(float)’: test_vf_float_conversions.cpp:63:20: error: expected primary-expression before ‘.’ token Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86939 Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* vc4: Interleave register allocation from regfile A and B.Eric Anholt2014-12-081-39/+38
| | | | | | | | | | | | | The register allocator prefers low-index registers from vc4_regs[] in the configuration we're using, which is good because it means we prioritize allocating the accumulators (which are faster). On the other hand, it was causing raddr conflicts because everything beyond r0-r2 ended up in regfile A until you got massive register pressure. By interleaving, we end up getting more instruction pairing from getting non-conflicting raddrs and QPU_WSes. total instructions in shared programs: 55957 -> 52719 (-5.79%) instructions in affected programs: 46855 -> 43617 (-6.91%)
* vc4: Fix decision for whether the MIN operation writes to the B regfile.Eric Anholt2014-12-081-3/+3
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* vc4: Drop dependency on r3 for color packing.Eric Anholt2014-12-081-4/+27
| | | | | | | | We can avoid it by carefully ordering the packing. This is important as a step in giving r3 to the register allocator. total instructions in shared programs: 56087 -> 55957 (-0.23%) instructions in affected programs: 18368 -> 18238 (-0.71%)
* vc4: Add support for GL 1.0 logic ops.Eric Anholt2014-12-081-2/+60
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* vc4: Add support for TGSI_OPCODE_UCMP.Eric Anholt2014-12-081-0/+12
| | | | This is being emitted now from st_glsl_to_tgsi.cpp.
* radeonsi/compute: Clamp COMPUTE_TMPRING_SIZE.WAVES to: num_cu * 32Tom Stellard2014-12-081-0/+3
| | | | This is the maximum value allowed for this field.
* winsys/radeon: Always report at least 1 compute unitTom Stellard2014-12-082-1/+3
| | | | | | | | All uses of this require that the value be at least one, so it's easier to report at least one than having to wrap all uses in MAX2(max_compute_units, 1). Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Program RASTER_CONFIG for harvested GPUs v5Tom Stellard2014-12-084-6/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Harvested GPUs have some of their render backends disabled, so in order to prevent the hardware from trying to render things with these disabled backends we need to correctly program the PA_SC_RASTER_CONFIG register. v2: - Write RASTER_CONFIG for all SEs. v3: - Set GRBM_GFX_INDEX.INSTANCE_BROADCAST_WRITES bit. - Set GRBM_GFX_INFEX.SH_BROADCAST_WRITES bit when done setting PA_SC_RASTER_CONFIG. - Get num_se and num_sh_per_se from kernel. v4: - Get correct value for num_se - Remove loop for setting PA_SC_RASTER_CONFIG - Only compute raster config when a backend has been disabled. v5: Michel Dänzer - Fix computation for chips with multiple SEs https://bugs.freedesktop.org/show_bug.cgi?id=60879 CC: "10.4 10.3" <[email protected]>
* draw: (trivial): remove double semicolonRoland Scheidegger2014-12-091-1/+1
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* st/mesa: For vertex shaders, don't emit saturate when SM 3.0 is unsupportedAbdiel Janulgue2014-12-082-4/+3
| | | | | | | | | | | There is a bug in the current lowering pass implementation where we lower saturate to clamp only for vertex shaders on drivers supporting SM 3.0. The correct behavior is to actually lower to clamp only when we don't support saturate which happens on drivers that don't support SM 3.0 Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* glsl: Don't optimize min/max into saturate when EmitNoSat is setAbdiel Janulgue2014-12-082-1/+2
| | | | | | | v3: Fix multi-line comment format (Ian) Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* ir_to_mesa: Remove sat to clamp lowering passAbdiel Janulgue2014-12-081-3/+1
| | | | | | | | | | | | | | | Fixes an infinite loop in swrast where the lowering pass unpacks saturate into clamp but the opt_algebraic pass tries to do the opposite. v3 (Ian): This is a revert of commit cfa8c1cb "ir_to_mesa: lower ir_unop_saturate" on the ir_to_mesa.cpp portion. prog_execute.c can handle saturates in vertex shaders, so classic swrast shouldn't need this lowering pass. Cc: "10.4" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83463 Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* loader: Add missing EXPAT_CFLAGS to libloader.la CPPFLAGSMichael Forney2014-12-081-1/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Remove default from brw_instruction_name switch to catch missing names.Matt Turner2014-12-081-12/+5
| | | | | | | The case-range extension is available in clang and gcc at least back to 3.4.0. Signed-off-by: Chris Forbes <[email protected]>
* i965: Add missing opcode names.Matt Turner2014-12-081-0/+9
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i965: Add opcode names for set_omask and set_sample_id.Matt Turner2014-12-081-0/+4
| | | | Reviewed-by: Chris Forbes <[email protected]>
* egl: Expose EGL_KHR_get_all_proc_addresses and its client extensionChad Versace2014-12-075-1/+23
| | | | | | | | | Mesa already implements the behavior of EGL_KHR_get_all_proc_addresses and EGL_KHR_client_get_all_proc_addresses. This patch just exposes the extension strings. See: https://www.khronos.org/registry/egl/extensions/KHR/EGL_KHR_get_all_proc_addresses.txt Signed-off-by: Chad Versace <[email protected]>
* docs: add news item and link release notes for mesa 10.3.5Emil Velikov2014-12-072-0/+7
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: Add sha256 sums for the 10.3.5 releaseEmil Velikov2014-12-071-1/+3
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 1ba2029184d3e7b013e3fc322e80a761604495d4)
* Add release notes for the 10.3.5 releaseEmil Velikov2014-12-071-0/+86
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit c90b0db1aef8f439b52b38ad58aac4ca202232a7)
* freedreno/a2xx: silence warning about missing DEPTH32XIlia Mirkin2014-12-061-1/+4
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: handle index_bias (i.e. base_vertex)Ilia Mirkin2014-12-061-3/+13
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: add bgr565 texturing and renderingIlia Mirkin2014-12-061-1/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: add support for SRGB render targetsIlia Mirkin2014-12-063-9/+13
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: output RGBA16_FLOAT from fs for certain outputsIlia Mirkin2014-12-063-1/+17
| | | | | | | Fixes R11G11B10F rendering, and is required for SRGB format support. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: re-enable rgb10_a2 render targetsIlia Mirkin2014-12-061-1/+3
| | | | | | | | There were previously regressions regarding border colors, which the updated swizzle logic resolves. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
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