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* radv: bitcast 16-bit outputs to integersRhys Perry2019-02-191-2/+2
| | | | | | | | | | 16-bit outputs are stored as 16-bit floats in the outputs array, so they have to be bitcast. Fixes: b722b29f10d ('radv: add support for 16bit input/output') Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 64065aa504c4872a15f7b0894b6037a6b2bcae65)
* v3d: Fix the check for "is the last thrsw inside control flow"Eric Anholt2019-02-192-8/+17
| | | | | | | | | | The execute.file check used to be good enough, until I stopped setting up the execute mask for uniform ifs. No known tests fixed, noticed while doing a refactor. Fixes: 080506057310 ("v3d: Handle dynamically uniform IF statements with uniform control flow.") (cherry picked from commit 441294962cd65d44febdbe9ef0b0d99b5d27cec8)
* v3d: Use the early_fragment_tests flag for the shader's disable-EZ field.Eric Anholt2019-02-194-17/+23
| | | | | | | | | | | | Apparently we need disable-EZ flagged, not just "does Z writes". Fixes dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_depth_fbo on 7278, even though it passed in simulation. Signed-off-by: Eric Anholt <[email protected]> Fixes: 051a41d3d56e ("v3d: Add support for the early_fragment_tests flag.") (cherry picked from commit cd5e0b272919a654079620adecd2abe24ff51233)
* radv: fix writing the alpha channel of MRT0 when alpha coverage is enabledSamuel Pitoiset2019-02-191-7/+8
| | | | | | | | | This version is better and safer. Cc: 18.3 19.0 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 47616810ed7cfce21d239391131ad9a5ef558b52)
* radv: write the alpha channel of MRT0 when alpha coverage is enabledSamuel Pitoiset2019-02-191-0/+8
| | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109597 Cc: 18.3 19.0 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 0d8f09629377da9cf48ab4315574d69fdef5369d)
* nir: Don't reassociate add/mul chains containing only constantsKenneth Graunke2019-02-191-5/+5
| | | | | | | | | | | | | | | | | | The idea here is to reassociate a * (b * c) into (a * c) * b, when b is a non-constant value, but a and c are constants, allowing them to be combined. But nothing was enforcing that 'b' must be non-constant, which meant that running opt_algebraic in a loop would never terminate if the IR contained non-folded constant expressions like 256 * 0.5 * 2. Normally, we call constant folding in such a loop too, but IMO it's better for nir_opt_algebraic to be robust and not rely on that. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109581 Fixes: 32e266a9a58 i965: Compile fp64 funcs only if we do not have 64-bit hardware support Reviewed-by: Ian Romanick <[email protected]> (cherry picked from commit 535251487ba56c4fd98465c4682881c2b9734242)
* intel/compiler/test: Add unit test for mismatched signedness comparisonMatt Turner2019-02-151-0/+32
| | | | | | | | | | v2 (idr): Move adding the test to after adding the fix. Reordering the two commits prevents possible headaches for git-bisect with scripts that always do 'ninja check'. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109404 Reviewed-by: Ian Romanick <[email protected]> (cherry picked from commit ac21dd4aee450b2a4bc63adb05356b07abba2ff6)
* intel/compiler: Avoid propagating inequality cmods if types are differentMatt Turner2019-02-151-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: Fix silly bug in logic. s/||/&&/ All but one of the affected shaders is in an Unreal4 demo. The other is in Tomb Raider. All of the cases that Ian investigated appear to be sequences like the following if (int(uint(some_float)) < 0) /* other relations too */ ... At least in Tomb Raider, it's not obvious that this sequence came from the original shader. In some of the Unreal demos, the shader contains code like if (int(uint(textureLod(...))) > 0) ... which explicitly generates the offending sequence. All Gen6+ platforms had similar results (Skylake shown): total instructions in shared programs: 15437170 -> 15437187 (<.01%) instructions in affected programs: 4492 -> 4509 (0.38%) helped: 0 HURT: 17 HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 0.05% max: 0.73% x̄: 0.66% x̃: 0.73% 95% mean confidence interval for instructions value: 1.00 1.00 95% mean confidence interval for instructions %-change: 0.57% 0.75% Instructions are HURT. total cycles in shared programs: 383007996 -> 383007992 (<.01%) cycles in affected programs: 20542 -> 20538 (-0.02%) helped: 6 HURT: 7 helped stats (abs) min: 2 max: 6 x̄: 5.33 x̃: 6 helped stats (rel) min: 0.11% max: 0.36% x̄: 0.32% x̃: 0.36% HURT stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4 HURT stats (rel) min: 0.27% max: 0.27% x̄: 0.27% x̃: 0.27% 95% mean confidence interval for cycles value: -3.30 2.69 95% mean confidence interval for cycles %-change: -0.19% 0.19% Inconclusive result (value mean confidence interval includes 0). No changes on Iron Lake or GM45. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109404 Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: [email protected] Tested-by: Danylo Piliaiev <[email protected]> (cherry picked from commit 2dff9a66b629834bffad47e7a9025e0f1de5ffc3)
* intel/fs: Bail in optimize_extract_to_float if we have modifiersJason Ekstrand2019-02-151-0/+9
| | | | | | | | | | | | | This fixes a bug in runscape where we were optimizing x >> 16 to an extract and then negating and converting to float. The NIR to fs pass was dropping the negate on the floor breaking a geometry shader and causing it to render nothing. Fixes: 1f862e923cb "i965/fs: Optimize float conversions of byte/word..." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109601 Tested-by: Lionel Landwerlin <[email protected]> Reviewed-by: Matt Turner <[email protected]> (cherry picked from commit 367b0ede4d9115aba772d6e46ec73642761f7ff6)
* swr: set PIPE_CAP_MAX_VARYINGS correctlyIlia Mirkin2019-02-151-0/+2
| | | | | | | | | | | | Unfortunately swr was missed in the original commit. The number of varyings should generally match up to what's reported as the shader caps for fragment inputs. Fixes: 6010d7b8e8be (gallium: add PIPE_CAP_MAX_VARYINGS) Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Alok Hota <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit 8c859367df95b74e7596f7fefffbdbf08bb8f8c7)
* anv: Put MOCS in the correct locationKenneth Graunke2019-02-151-2/+2
| | | | | | | | | | | | My patch to switch from struct-based MOCS to numeric MOCS accidentally divided all MOCS entries by 2 in the Vulkan driver. MOCS on Gen9+ is just an array index into a table. But in the hardware packets, the index starts at bit 1. So we need to shift it. Fixes: 0b44644ca68 (genxml: Consistently use a numeric "MOCS" field) Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit 39aee57523a02552e7eae7df5da488e535aeb1eb)
* spirv: Add missing breakIan Romanick2019-02-141-0/+1
| | | | | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Fixes: c6465fec0c5 ("spirv: add SpvCapabilityInt64Atomics") CID: 1442555 (cherry picked from commit 9a918050e0886d8c6d6adc0c687ffd30d8f70b40)
* meson: Add dependency on genxml to anvilDylan Baker2019-02-141-2/+5
| | | | | | | | | | | | | Currently the Intel "anvil" driver races with the generation of genxml files, while i965 has an explicit dependency. This patch adds the same dependency to anvil. Fixes: d1992255bb29054fa51763376d125183a9f602f ("meson: Add build Intel "anv" vulkan driver") Acked-by: Jason Ekstrand <[email protected]> Acked-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> (cherry picked from commit 279060cd32dd673c6a5bf302ceac852f51a6c17c)
* radv: always export gl_SampleMask when the fragment shader uses itSamuel Pitoiset2019-02-141-4/+4
| | | | | | | | | | For some reasons, this breaks trees rendering in Project Cars. Fixes: 85010585cde ("radv: only enable gl_SampleMask if MSAA is enabled too") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109401 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 334da034d8d91ca5a0a1bff8deaefd8ca762c42e)
* radv/winsys: fix BO list creation when RADV_DEBUG=allbos is setSamuel Pitoiset2019-02-141-0/+1
| | | | | | | Fixes: 50fd253bd6e ("radv/winsys: Add priority handling during submit.") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 5e18000d1b070ecf627138b7bff47ff8fef81576)
* get-pick-list: Add --pretty=medium to the arguments for Cc patchesDylan Baker2019-02-131-2/+2
| | | | | | | | | | | | | | | Because none of them have been picked up for 19.0 due to this bug being reintroduced. v2: - Fix fixes tags Fixes: e6b3a3b2014413366110f6deeced8095e7262b1d ("bin/get-pick-list.sh: handle "typod" usecase.") Fixes: fac10169bbad2da918ef07a62c01e0b321508cfe ("bin/get-pick-list.sh: prefix output with "[stable] "") Reviewed-by: Andres Gomez <[email protected]> Reviewed-by: Emil Velikov <[email protected]> (cherry picked from commit aff52dd2c61eb8d1b03cebbcca7e070ffa48afdf)
* nir/opt_if: don't mark progress if nothing changesKarol Herbst2019-02-131-0/+7
| | | | | | | | | | | | | | | | | | | | | if we have something like this: loop { ... if x { break; } else { continue; } } opt_if_loop_last_continue returns true marking progress allthough nothing changes. Fixes: 5921a19d4b0c6 "nir: add if opt opt_if_loop_last_continue()" Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit 7e08f22a72cfc379902feeca3673db6aa344f782)
* radeonsi: Fix guardband computation for large render targetsOscar Blumberg2019-02-131-2/+28
| | | | | | | | | | Stop using 12.12 quantization for viewports that are not contained in the lower 4k corner of the render target as the hardware needs to keep both absolute and relative coordinates representable. Signed-off-by: Marek Olšák <[email protected]> Cc: 18.3 19.0 <[email protected]> (cherry picked from commit 3c540e0a748844258e77254fc4f864f3b875fe18)
* version: bump for 19.0-rc4mesa-19.0.0-rc4Dylan Baker2019-02-131-1/+1
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* anv/cmd_buffer: check for NULL framebufferJuan A. Suarez Romero2019-02-121-5/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This can happen when we record a VkCmdDraw in a secondary buffer that was created inheriting from the primary buffer, but with the framebuffer set to NULL in the VkCommandBufferInheritanceInfo. Vulkan 1.1.81 spec says that "the application must ensure (using scissor if neccesary) that all rendering is contained in the render area [...] [which] must be contained within the framebuffer dimesions". While this should be done by the application, commit 465e5a86 added the clamp to the framebuffer size, in case of application does not do it. But this requires to know the framebuffer dimensions. If we do not have a framebuffer at that moment, the best compromise we can do is to just apply the scissor as it is, and let the application to ensure the rendering is contained in the render area. v2: do not clamp to framebuffer if there isn't a framebuffer v3 (Jason): - clamp earlier in the conditional - clamp to render area if command buffer is primary v4: clamp also x and y to render area (Jason) v5: rename used variables (Jason) Fixes: 465e5a86 ("anv: Clamp scissors to the framebuffer boundary") CC: Jason Ekstrand <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit 1ad26f941792f07f226c054811be78b0c0ac9fce)
* radv: fix using LOAD_CONTEXT_REG with old GFX ME firmwares on GFX8Samuel Pitoiset2019-02-123-3/+10
| | | | | | | | | | This fixes a critical issue. Cc: <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109575 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 1b8983c25be19073c02fe9630e949be55f8280fa)
* radv: fix compiler issues with GCC 9Samuel Pitoiset2019-02-121-42/+48
| | | | | | | | | | | | | | | | | | "The C standard says that compound literals which occur inside of the body of a function have automatic storage duration associated with the enclosing block. Older GCC releases were putting such compound literals into the scope of the whole function, so their lifetime actually ended at the end of containing function. This has been fixed in GCC 9. Code that relied on this extended lifetime needs to be fixed, move the compound literals to whatever scope they need to accessible in." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109543 Cc: <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Gustaw Smolarczyk <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 129a9f4937b8f2adb4d37999677d748d816d611c)
* st/mesa: Limit GL_MAX_[NATIVE_]PROGRAM_PARAMETERS_ARB to 2048Kenneth Graunke2019-02-121-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Piglit's vp-max-array test creates a vertex program containing a uniform array sized to the value of GL_MAX_NATIVE_PROGRAM_PARAMETERS_ARB. Mesa will then add additional state-var parameters for things like the MVP matrix. radeonsi currently exposes a value of 4096, derived from constant buffer upload size. This means the array will have 4096 elements, and the extra MVP state-vars would get a prog_src_register::Index of over 4096. Unfortunately, prog_src_register::Index is a signed 13-bit integer, so values beyond 4096 end up turning into negative numbers. Negative source indexes are only valid for relative addressing, so this ends up generating illegal IR. In prog_to_nir, this would cause an out of bounds array access. st_mesa_to_tgsi checks for a negative value, assumes it's bogus, and remaps it to parameter 0 in order to get something in-range. This isn't right - instead of reading the MVP matrix, it would read the first element of the vertex program's large array. But the test only checks that the program compiles, so we never noticed that it was broken. This patch limits the size of the program limits, with the understanding that we may need to generate additional state-vars internally. i965 has exposed 1024 for this limit for years, so I don't expect lowering it to 2048 will cause any practical problems for radeonsi or other drivers. Fixes vp-max-array with prog_to_nir.c. Cc: "19.0" <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit f45dd6d31b2ff46a082931386ccd0bf043cfad59)
* st/va/vp9: set max reference as default of VP9 reference numberLeo Liu2019-02-121-1/+6
| | | | | | | | | If there is no information about number of render targets Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit a0a52a036708dbf5989778795fd67a79e3226289)
* st/va: fix the incorrect max profiles reportLeo Liu2019-02-122-2/+3
| | | | | | | | | | | | Add "PIPE_VIDEO_PROFILE_MAX" to enum, so it will make sure here will be correct when adding more profiles in the future. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109107 Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit 21cdb828a3f4d1e2f140fc7c81a4bc305b2f6b04)
* winsys/amdgpu: don't drop manually added fence dependenciesMarek Olšák2019-02-121-2/+0
| | | | | | | | wow, it's hard to believe that fence and syncobjs dependencies were ignored. Cc: 18.3 19.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> (cherry picked from commit ddfe209a0d61917e7b08100eeac82f4c20ca59e8)
* radeonsi: fix EXPLICIT_FLUSH for flush offsets > 0Marek Olšák2019-02-121-2/+5
| | | | | | Cc: 18.3 19.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> (cherry picked from commit 61c678d4bc91d2ff9ca8c9b183e08daf07d8d24c)
* gallium/u_threaded: fix EXPLICIT_FLUSH for flush offsets > 0Marek Olšák2019-02-121-1/+2
| | | | | | Cc: 18.3 19.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> (cherry picked from commit 4522f01d4ef9e8a1bb945ca28fba7649aae2171b)
* nvc0: we have 16k-sized framebuffers, fix default scissorsIlia Mirkin2019-02-121-2/+2
| | | | | | | | | | For some reason we don't use view volume clipping by default, and use scissors instead. These scissors were set to an 8k max fb size, while the driver advertises 16k-sized framebuffers. Signed-off-by: Ilia Mirkin <[email protected]> Cc: <[email protected]> (cherry picked from commit cc79a1483ffb7b91edc97c9870eadcab1e83b8f3)
* st/mesa: require RGBA2, RGB4, and RGBA4 to be renderableKarol Herbst2019-02-121-0/+2
| | | | | | | | | | | | | If the driver does not support rendering to these formats but does support texturing, we can end up in incompatibilities between textures and renderbuffers that are then copied to. Fixes KHR-GL45.copy_image.functional on nvc0 Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit cbd1ad6165f0aea7fb7c6fd1b36ad5317dd65cb7)
* gallium: add PIPE_CAP_MAX_VARYINGSKarol Herbst2019-02-1218-16/+51
| | | | | | | | | | | | | | | | | | | Some NVIDIA hardware can accept 128 fragment shader input components, but only have up to 124 varying-interpolated input components. We add a new cap to express this cleanly. For most drivers, this will have the same value as PIPE_SHADER_CAP_MAX_INPUTS for the fragment shader. Fixes KHR-GL45.limits.max_fragment_input_components Conflicts resolved by Dylan Signed-off-by: Karol Herbst <[email protected]> [imirkin: rebased, improved docs/commit message] Signed-off-by: Ilia Mirkin <[email protected]> Acked-by: Rob Clark <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit 6010d7b8e8bee1bcea2b329cf6d3b44c5fc3ca66)
* gm107/ir: add fp64 rsqKarol Herbst2019-02-123-3/+128
| | | | | | Acked-by: Ilia Mirkin <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit cce495572136a606dd2a35e79f45080c3796e2cc)
* gm107/ir: add fp64 rcpKarol Herbst2019-02-123-4/+270
| | | | | | Acked-by: Ilia Mirkin <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit 815a8e59c6d462a7008653ea9e3010d40b6ba589)
* gk104/ir: Use the new rcp/rsq in libraryKarol Herbst2019-02-123-15/+334
| | | | | | | | [imirkin: add a few more "long" prefixes to safen things up] Acked-by: Ilia Mirkin <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit 12669d29705a26478aa691cb454149628be65f17)
* gk110/ir: Use the new rcp/rsq in libraryBoyan Ding2019-02-125-0/+42
| | | | | | | | | | | v2: (Karol Herbst <[email protected]> * fix Value setup for the builtins Signed-off-by: Boyan Ding <[email protected]> [imirkin: track the fp64 flag when switching ops to calls] Signed-off-by: Ilia Mirkin <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit 656ad060518d067a3b311db8c2de2a396fb41898)
* gk110/ir: Add rsq f64 implementationBoyan Ding2019-02-122-2/+109
| | | | | | | Signed-off-by: Boyan Ding <[email protected]> Acked-by: Ilia Mirkin <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit 7937408052a1896f0b08b0110bb8a1790eeee351)
* gk110/ir: Add rcp f64 implementationBoyan Ding2019-02-122-4/+235
| | | | | | | Signed-off-by: Boyan Ding <[email protected]> Acked-by: Ilia Mirkin <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit 04593d9a73ea257a36cc3b9fb5cd41427beaaea5)
* nvc0: stick zero values for the compute invocation countsIlia Mirkin2019-02-121-0/+2
| | | | | | | | | | | Not quite perfect, but at least we don't end up with random values in the query buffer. Fixes KHR-GL45.pipeline_statistics_query_tests_ARB.functional_default_qo_values Signed-off-by: Ilia Mirkin <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit 6adb9b38bfb1f6ee4c94596bf0744225aa8e967a)
* nv50,nvc0: use condition for occlusion queries when already completeIlia Mirkin2019-02-126-28/+25
| | | | | | | | | | | | | | | | | | | For the NO_WAIT variants, we would jump into the ALWAYS case for both nested and inverted occlusion queries. However if the query had previously completed, the application could reasonably expect that the render condition would follow that result. To resolve this, we remove the nesting distinction which unnecessarily created an imbalance between the regular and inverted cases (since there's no "zero" condition mode). We also use the proper comparison if we know that the query has completed (which could happen as a result of an earlier get_query_result call). Fixes KHR-GL45.conditional_render_inverted.functional Signed-off-by: Ilia Mirkin <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit e00799d3dc0595dc3998dbf199ceec8b1eece966)
* nvc0: fix 3d images on keplerIlia Mirkin2019-02-122-35/+34
| | | | | | | | | | | | | | Looks like SUBFM.3D and SUEAU are perfectly capable of dealing with 3d tiling, they just need the correct inputs. Supply them. We also have to deal with the case where a 2d "layer" of a 3d image is bound. In this case, we supply the z coordinate separately to the shader, which has to optionally treat every 2d case as if it could be a slice of a 3d texture. Signed-off-by: Ilia Mirkin <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit 162352e6711b3ceab114686f7a3248074339e7f7)
* nvc0/ir: always use CG mode for loads from atomic-only buffersIlia Mirkin2019-02-121-2/+12
| | | | | | | | | | | | | | | | | Atomic operations don't update the local cache, which means that we would have to issue CCTL operations in order to get the updated values. When we know that a buffer is primarily used for atomic operations, it's easier to just avoid the caching at that level entirely. The same issue persists for non-atomic buffers, which will have to be fixed separately. Fixes the failing dEQP-GLES31.functional.atomic_counter.* tests. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit 4443b6ddf2e08d06f3d0457cf20a2e04244cde37)
* nvc0: add support for handling indirect draws with attrib conversionIlia Mirkin2019-02-123-1/+82
| | | | | | | | | | | | | | | | | The hardware does not natively support FIXED and DOUBLE formats. If those are used in an indirect draw, they have to be converted. Our conversion tries to be clever about only converting the data that's needed. However for indirect, that won't work. Given that DOUBLE or FIXED are highly unlikely to ever be used with indirect draws, read the indirect buffer on the CPU and issue draws directly. Fixes the failing dEQP-GLES31.functional.draw_indirect.random.* tests. Signed-off-by: Ilia Mirkin <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit 399215eb7a0517463e5757c598d6cff6ae2301d0)
* amd/common: Use correct writemask for shared memory stores.Bas Nieuwenhuizen2019-02-121-1/+1
| | | | | | | | The check was for 1 bit being set, which is clearly not what we want. CC: <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 3c24fc64c7a4e564d84843fab7db25963d574d99)
* radv: Only look at pImmutableSamples if the descriptor has a sampler.Bas Nieuwenhuizen2019-02-121-2/+6
| | | | | | | | Equivalent of ANV patch c7f4a2867ce492d78c1f8e2870c0a593d280572d CC: <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 39ab4e12f71a640b43403a110d3d85565b59d16c)
* gallium-xlib: query MIT-SHM before using it.Bart Oldeman2019-02-121-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | When Mesa is compiled for gallium-xlib using e.g. ./configure --enable-glx=gallium-xlib --disable-dri --disable-gbm -disable-egl and is used by an X server (usually remotely via SSH X11 forwarding) that does not support MIT-SHM such as XMing or MobaXterm, OpenGL clients report error messages such as Xlib: extension "MIT-SHM" missing on display "localhost:11.0". ad infinitum. The reason is that the code in src/gallium/winsys/sw/xlib uses MIT-SHM without checking for its existence, unlike the code in src/glx/drisw_glx.c and src/mesa/drivers/x11/xm_api.c. I copied the same check using XQueryExtension, and tested with glxgears on MobaXterm. This issue was reported before here: https://lists.freedesktop.org/archives/mesa-users/2016-July/001183.html Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Cc: <[email protected]> (cherry picked from commit a203eaa4f4fb672b95426289b8dad3a8998f92d7)
* nv50,nvc0: add explicit settings for recent capsIlia Mirkin2019-02-122-0/+4
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit 38f542783faa360020b77fdd76b97f207a9e0068)
* meson: drop the xcb-xrandr version requirementMarek Olšák2019-02-121-1/+1
| | | | | | | | autotools doesn't have any requirement. This fixes meson on Ubuntu 16.04. Cc: 18.3 19.0 <[email protected]> Reviewed-by: Erik Faye-Lund <[email protected]> (cherry picked from commit 1e85cfb91a08565f28f51cc19573324722765823)
* Bump version for 19.0-rc3mesa-19.0.0-rc3Dylan Baker2019-02-121-1/+1
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* Revert "intel/compiler: More peephole select"Dylan Baker2019-02-121-14/+1
| | | | This reverts commit 8fb8ebfbb05d3323481c8ba6d320b3a3580bad99.
* Revert "nir/opt_peephole_select: Don't peephole_select expensive math ↵Dylan Baker2019-02-1210-41/+18
| | | | | | | | | | instructions" This reverts commit 378f9967710e9145f2a4f8eee89d87badbe0e6ea. This also remove the default true argument from the a2xx nir backend, which was introduced after this commit. There should be no change in functionality.
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