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* mesa: translate into gallium vertex formats in mesa/mainMarek Olšák2020-02-143-261/+259
| | | | | Reviewed-by: Mathias Fröhlich <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
* intel/fs/gen7+: Implement discard/demote for SIMD32 programs.Francisco Jerez2020-02-142-8/+14
| | | | | | | | | | | At this point this simply involves fixing the initialization of the sample mask flag register to take the right dispatch mask from the thread payload, and fixing sample_mask_reg() to return f1.1 for the second half of a SIMD32 thread. This improves Manhattan 3.1 performance by 2.4%±0.31% (N>40) on my ICL with SIMD32 enabled relative to falling back to SIMD16 for the shaders that use discard. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Return consistent UW types from sample_mask_reg() in fragment shaders.Francisco Jerez2020-02-141-3/+2
| | | | | | | | | In SIMD32 programs that don't use discard, the upper 16 bits of the UD result of sample_mask_reg() don't contain the sample mask of the upper 16 channels as one would expect. Stop pretending we are returning a valid 32-bit mask. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Refactor predication on sample mask into helper function.Francisco Jerez2020-02-141-34/+44
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs/gen7+: Swap sample mask flag register and FIND_LIVE_CHANNEL temporary.Francisco Jerez2020-02-144-13/+18
| | | | | | | | | | | | | FIND_LIVE_CHANNEL was using f1.0-f1.1 as temporary flag register on Gen7, instead use f0.0-f0.1. In order to avoid collision with the discard sample mask, move the latter to f1.0-f1.1. This makes room for keeping track of the sample mask of the second half of SIMD32 programs that use discard. Note that some MOVs of the sample mask into f1.0 become redundant now in lower_surface_logical_send() and lower_a64_logical_send(). Reviewed-by: Kenneth Graunke <[email protected]>x
* intel/fs: Use helper for discard sample mask flag subregister number.Francisco Jerez2020-02-144-5/+16
| | | | | | | | | Use it instead of hard-coding f0.1 for the sample mask of programs that use discard. This will make the task easier when we replace f0.1 with another flag register location in order to support discard with SIMD32 shaders. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Make sample_mask_reg() local to brw_fs.cpp and use it in more places.Francisco Jerez2020-02-142-24/+28
| | | | | | | | It's only really useful there. This will avoid confusion with another helper with a similar purpose I'm about to introduce that will be useful in multiple files from the FS back-end. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs/gen11: Work around dual-source blending hangs in combination with ↵Francisco Jerez2020-02-141-0/+12
| | | | | | | | | | | | | | SIMD32. The SIMD8 dual-source blending framebuffer write messages seem to have trouble releasing the pixel scoreboard dependency in SIMD32 dispatch mode, which leads to hangs. I have a better workaround for this which doesn't involve disabling SIMD32 when dual-source blending is enabled, but I'm still investigating some issues with it. Limit the dispatch width to SIMD16 in such cases for the moment in order to make the CI happy on ICL with SIMD32 fragment shaders enabled. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Set src0 alpha present bit in header when provided in message payload.Francisco Jerez2020-02-143-15/+6
| | | | | | | | | | | | | | | | | | Currently the "Source0 Alpha Present to RenderTarget" bit of the RT write message header is derived from brw_wm_prog_data::replicate_alpha. However the src0_alpha payload is provided anytime it's specified to the logical message. This could theoretically lead to an inconsistency if somebody provided a src0_alpha value while brw_wm_prog_data::replicate_alpha was false, as I'm planning to do in a future commit in order to implement a hardware workaround. Instead calculate the header bit based on whether a src0_alpha value was provided to the logical message, which guarantees the same behavior on pre-ICL and ICL+ (the latter used an extended descriptor bit for this which didn't suffer from the same issue). Remove the brw_wm_prog_data::replicate_alpha flag. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs/gen12: Workaround data coherency issues due to broken NoMask ↵Francisco Jerez2020-02-141-34/+100
| | | | | | | | | | | | | | | | | | | | | | | | control flow. Together with the fixup_nomask_control_flow() pass introduced in a previous patch, this implements a less invasive alternative to the workaround documented in the hardware spec for GEN:BUG:1407528679, which doesn't involve disabling structured control flow. Under some conditions Gen12 hardware can end up executing a BB with all channels disabled, which will lead to the execution of any NoMask instructions in it, even though any execution-masked instructions will be correctly shot down. This could break assumptions of the SWSB pass if the data computed by a NoMask instruction is synchronized against by using an SWSB annotation baked into a regular execution-masked instruction, since the first (NoMask) instruction may be executed redundantly by the hardware, even though the second will correctly be shot down, potentially leading to a RaW or WaW hazard if a third instruction subsequently accesses the destination register of the first instruction. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Cc: 20.0 <[email protected]>
* intel/fs/gen12: Fixup/simplify SWSB annotations of SIMD32 scratch writes.Francisco Jerez2020-02-141-7/+3
| | | | | | | | | | | | | Found by inspection. Existing code was trying to avoid assuming that an SBID had been assigned to the virtual instruction, but synchronizing the header setup with respect to the previous SIMD16 SEND by using SYNC.ALLRD doesn't really seem possible unless the SEND instruction had been assigned an SBID. Assert-fail instead if no SBID has been allocated. Fixes: 15e3a0d9d264becc "intel/eu/gen12: Set SWSB annotations in hand-crafted assembly." Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Cc: 20.0 <[email protected]>
* intel/fs/gen12: Workaround unwanted SEND execution due to broken NoMask ↵Francisco Jerez2020-02-142-0/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | control flow. This is a less invasive alternative to the workaround documented in the hardware spec for GEN:BUG:1407528679, which doesn't involve disabling structured control flow (it's unlikely that switching to GOTO/JOIN would have actually fixed the problem anyway). Under some conditions Gen12 hardware can end up executing a BB with all channels disabled, which will lead to the execution of any NoMask instructions in it, even though any execution-masked instructions will be correctly shot down. This may break assumptions of some NoMask SEND messages whose descriptor depends on data generated by live invocations of the shader. This avoids the problem by predicating certain instructions on an ANY horizontal predicate that makes sure that their execution is omitted when all channels of the program are disabled. The shader-db impact of this patch seems to be minimal: total instructions in shared programs: 17169833 -> 17169913 (0.00%) instructions in affected programs: 30663 -> 30743 (0.26%) helped: 0 HURT: 42 total cycles in shared programs: 336966176 -> 336968568 (0.00%) cycles in affected programs: 2367290 -> 2369682 (0.10%) helped: 0 HURT: 13 Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Cc: 20.0 <[email protected]>
* intel/fs: Add virtual instruction to load mask of live channels into flag ↵Francisco Jerez2020-02-145-2/+22
| | | | | | | register. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Cc: 20.0 <[email protected]>
* intel/fs/gen7: Fix fs_inst::flags_written() for SHADER_OPCODE_FIND_LIVE_CHANNEL.Francisco Jerez2020-02-141-1/+2
| | | | | | | | | | We need to pass a width of 32 since the opcode bashes the whole f1.0 register on IVB. This is unlikely to have caused problems since f1.0 is largely unused currently. That's likely to change soon though, even on platforms other than Gen7. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Cc: 20.0 <[email protected]>
* intel/fs/cse: Make HALT instruction act as CSE barrier.Francisco Jerez2020-02-141-0/+10
| | | | | | | | | | | | | Found by inspection. This seems particularly likely to cause problems with instructions dependent on the current execution mask like SHADER_OPCODE_FIND_LIVE_CHANNEL or the FS_OPCODE_LOAD_LIVE_CHANNELS instruction I'm about to introduce, but one could imagine it leading to data corruption if CSE ever managed to combine two instructions before and after the FS_OPCODE_PLACEHOLDER_HALT, since the one before may not be executed for some channels. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Cc: 20.0 <[email protected]>
* lima/parser: Extend rsw parsing showing strings instead of numbersAndreas Baierl2020-02-142-22/+131
| | | | | | | Reviewed-by: Vasily Khoruzhick <[email protected]> Signed-off-by: Andreas Baierl <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3807> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3807>
* radeonsi: don't wait for shader compilation to finish when destroying a contextMarek Olšák2020-02-141-3/+0
| | | | | | | | | | | | This was a hack for glsl_types deinitialization and it predates the proper fix, which was the addition of glsl_type_singleton_decref. This fixes a crash when the context is destroyed via the atexit handler. Cc: 19.3 20.0 <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3800> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3800>
* egl: directly access static members instead of using _egl{Get,Set}ConfigKey()Eric Engestrom2020-02-143-42/+38
| | | | | | | | | | | | This function is meant for when the attribute is unknown at compile-time (eg. user-specified), but in all these cases it is much simpler to just read/write the member directly. Suggested-by: Emil Velikov <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3816> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3816>
* freedreno/a6xx: document some unknown bitsJonathan Marek2020-02-143-4/+12
| | | | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3814> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3814>
* freedreno: name sysmem color/depth flush eventsJonathan Marek2020-02-148-23/+24
| | | | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3814>
* panfrost: Simplify swizzle translationAlyssa Rosenzweig2020-02-141-32/+5
| | | | | | | | | It lines up anyway, and Gallium shouldn't change this. (And if it does, we'll deal with that then since CI would start failing.) Signed-off-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3824> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3824>
* panfrost: Inline panfrost_get_default_swizzleIcecream952020-02-145-20/+23
| | | | | | | | | | | This commit replaces panfrost_get_default_swizzle with an inlined implementation where the returned values can be determined at compile time. According to perf, this previously used about 2% CPU for Openarena. Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3824>
* spirv2nir: Add kernel spirv supportElie Tournier2020-02-141-1/+65
| | | | | | | Signed-off-by: Elie Tournier <[email protected]> Reviewed-by: Erik Faye-Lund <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3678> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3678>
* spirv2nir: print nir shader if translation succedElie Tournier2020-02-141-1/+5
| | | | | | Signed-off-by: Elie Tournier <[email protected]> Reviewed-by: Erik Faye-Lund <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3678>
* zink: do not use SpvDimRectErik Faye-Lund2020-02-142-2/+2
| | | | | | | | Vulkan doesn't support SpvDimRect. But we don't need to pass this at all, as we already mark the sampler as un-normalized. Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3764> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3764>
* lima: handle early-z and pixel kill betterVasily Khoruzhick2020-02-141-5/+19
| | | | | | | | | | | | | | | | | | [1] calls bit 12 of aux0 'pixel kill' which is likely forward pixel kill described in [2]. Blob sets this bit if early-z is enabled and blending is disabled and colormask is RGBA. Bit 8 seems to be always enabled with bit 9 (early-z). Let's mimic blob behavior. [1] https://web.archive.org/web/20171026123213/http://limadriver.org/Render_State/ [2] https://community.arm.com/developer/tools-software/graphics/b/blog/posts/killing-pixels---a-new-optimization-for-shading-on-arm-mali-gpus Reviewed-by: Andreas Baierl <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3754> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3754>
* gitlab-ci: Add three more dEQP-GLES31 tests to softpipe skipsMichel Dänzer2020-02-142-2/+3
| | | | | | | | | | | These have randomly flipped lately, see e.g. https://gitlab.freedesktop.org/mesa/mesa/-/jobs/1620056 https://gitlab.freedesktop.org/daenzer/mesa/-/jobs/1621374 https://gitlab.freedesktop.org/daenzer/mesa/-/jobs/1622156 Reviewed-by: Eric Anholt <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3811> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3811>
* gitlab-ci: Sort random failure softpipe skipsMichel Dänzer2020-02-141-3/+2
| | | | | Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3811>
* docs/new_features: empty the feature list for the 20.1 cycleSamuel Pitoiset2020-02-141-19/+0
| | | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3793> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3793>
* radv: remove unnecessary RADV_DEBUG=nobatchchain optionSamuel Pitoiset2020-02-146-17/+11
| | | | | | | | | It was used in the past but nowadays chained submissions work fine. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3791> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3791>
* glsl: fix gl_nir_set_uniform_initializers() for image arraysTimothy Arceri2020-02-141-1/+1
| | | | | | | | | | | | | The if was incorrectly checking for an image type on what could be an array of images. Here we change it to use the type stored in uniform storage which has already been stripped of arrays, this is what the above code for samplers does also. Fixes: 2bf91733fcb5 ("nir/linker: Set the uniform initial values") Reviewed-by: Alejandro Piñeiro <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3757> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3757>
* intel/tools: Update aubinator_error_decode.Rafael Antognolli2020-02-131-0/+2
| | | | | | | | | | "ringbuffer" is now called only "ring" in the error state. v2: Keep compatible with old error state (Lionel). v3: Also update "gtt_offset" -> "batch". Closes: https://gitlab.freedesktop.org/drm/intel/issues/1206 Reviewed-by: Lionel Landwerlin <[email protected]>
* freedreno: allow INVALID modifierRob Clark2020-02-131-0/+1
| | | | | | | | | | | | | Re-allow INVALID modifier in import path. The legacy import path (createImageFromFds()), which is used by android, uses the INVALID modifier. Previously we would ignore this and just setup the imported buffer as linear. Restore this behavior to unbreak the legacy import path. Fixes: 9891062642a freedreno/a6xx: Implement layout for DRM_FORMAT_MOD_QCOM_COMPRESSED Signed-off-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3817> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3817>
* intel/isl: Switch to R8_UNORM format for compatiblitySagar Ghuge2020-02-131-0/+9
| | | | | | | | | | | | | | | | | | | | | | | Gen12 added CCS_E support for A8_UNORM. Intercept A8_UNORM format and switch to R8_UNORM, as both share the same aux map format encoding so they are compatible. Fixes Piglit's ext_framebuffer_multisample-formats all_samples, which was hitting an assert about A8_UNORM and R8_UINT not being CCS_E compatible formats. v2: Add gen check (Kenneth Graunke) v3: Intercept A8_UNORM and set format to R8_UNORM (Jason Ekstrand) v4: - Remove gen check and move block little bit down (Jason Ekstrand) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3719> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3719>
* intel/isl: Move get_format_encoding function to islSagar Ghuge2020-02-133-73/+75
| | | | | | | | | | | | | | | Move get_format_encoding function to isl and rename to isl_get_aux_map_format_encoding. v2: - Rename isl_get_aux_map_format_encoding to isl_format_get_aux_map_encoding (Jason Ekstrand) Signed-off-by: Sagar Ghuge <[email protected]> Suggested-by: Kenneth Graunke <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3719>
* Revert "gitlab-ci: disable a630 tests as mesa-cheza is down (again)"Fritz Koenig2020-02-131-6/+6
| | | | | | | This reverts commit 18657c0c0a9074d3dfc0763b396929bcf34f71b4 Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3804> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3804>
* freedreno/a6xx: fix Z24_UNORM_S8_UINT_AS_R8G8B8A8Jonathan Marek2020-02-131-1/+1
| | | | | | | | | | | | | | | CI didn't run so missed this. Note previously had : texfmt = TFMT6_Z24_UNORM_S8_UINT rbfmt = RB6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 which are both now FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 Fixes: 18786cc7d55 ("freedreno/a6xx: use single format enum") Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3804>
* iris: add support INTEL_blackhole_renderLionel Landwerlin2020-02-134-0/+69
| | | | | | | | | | | | | | | v2: Use a software mechanism to manage blackhole state v3: s/iris_batchbuffer/iris_batch/ (Ken) v4: Fixup state transition mistake (Ken/Lionel) v5: Cleanup iris_batch_flush (Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2964> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2964>
* st: add support for INTEL_blackhole_renderLionel Landwerlin2020-02-135-0/+21
| | | | | | | | | | | | | | | | Adding a new CSO proved to be fairly difficult especially because this extension affect draw/dispatch/blit alike. Instead this change passes the state of the noop into the entry points emitting the operations affected. v2: Fix assert in default pipe caps v3: Drop whitespace changes (Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2964>
* i965: enable INTEL_blackhole_renderLionel Landwerlin2020-02-135-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: condition the extension on context isolation support from the kernel (Chris) v3: (Lionel) The initial version of this change used a feature of the Gen7+ command parser to turn the primitive instructions into no-ops. Unfortunately this doesn't play well with how we're using the hardware outside of the user submitted commands. For example resolves are implicit operations which should not be turned into no-ops as part of the previously submitted commands (before blackhole_render is enabled) might not be disabled. For example this sequence : glClear(); glEnable(GL_BLACKHOLE_RENDER_INTEL); glDrawArrays(...); glReadPixels(...); glDisable(GL_BLACKHOLE_RENDER_INTEL); While clear has been emitted outside the blackhole render, it should still be resolved properly in the read pixels. Hence we need to be more selective and only disable user submitted commands. This v3 manually turns primitives into MI_NOOP if blackhole render is enabled. This lets us enable this feature on any platform. v4: Limit support to gen7.5+ (Lionel) v5: Enable Gen7.5 support again, requires a kernel update of the command parser (Lionel) v6: Disable Gen7.5 again... Kernel devs want these patches landed before they accept the kernel patches to whitelist INSTPM (Lionel) v7: Simplify change by never holding noop (there was a shortcoming in the test not considering fast clears) Only program register using MI_LRI (Lionel) v8: Switch to software managed blackhole (BDW hangs on compute batches...) v9: Simplify the noop state tracking (Lionel) v10: Don't modify flush function (Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> (v8) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2964>
* mesa: add INTEL_blackhole_renderLionel Landwerlin2020-02-133-0/+17
| | | | | | | | | | | | | | | v2: Implement missing Enable/Disable (Emil) v3: Drop unused NewIntelBlackholeRender (Ken) v4: Bring back NewIntelBlackholeRender as i965 implementation uses it again (Lionel) v5: Drop atom (Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2964>
* Revert "st/va: Convert interlaced NV12 to progressive"Thong Thai2020-02-131-51/+4
| | | | | | | | | | | This reverts commit 2add63060b51ea2ae432d10e1bd52d6cc0a4dcbb. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2454 Fixes: 2add63060b51 "st/va: Convert interlaced NV12 to progressive" Signed-off-by: Thong Thai <[email protected]> Acked-by: Leo Liu <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3815> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3815>
* anv: Reject modifiers on depth/stencil formatsJason Ekstrand2020-02-131-3/+7
| | | | | | | | | | | | | | 6790397346cc added code which attempts to reject modifiers on depth/stencil formats but it was placed after the early return for depth and stencil aspects. This commit moves it up so it actually works. Of course, this doesn't actually matter because the only user of any of the modifiers stuff is the WSI code and it will never do anything with depth/stencil. Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3794> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3794>
* gallium/swr: fix rdtsc debug statistics mechanismKrzysztof Raszkowski2020-02-139-58/+44
| | | | | | Reviewed-by: Jan Zielinski <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3812> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3812>
* gitlab-ci: remove load_store_vectorizer from expected s390x test failuresRhys Perry2020-02-131-1/+0
| | | | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3690> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3690>
* nir: fix nir_const_value_as_uint bit size in load/store vectorizer testsRhys Perry2020-02-132-4/+6
| | | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3690>
* Revert "nir: Add a couple trivial abs optimizations"Erik Faye-Lund2020-02-131-2/+0
| | | | | | | | | | | | | These were already added in 9fdaeb7776c ("nir: add min/max optimisation"), and there's no point in doing them twice. This reverts commit e4d346c86db0ae332fcdf55eac0e075cfb99a7eb. Fixes: e4d346c86db ("nir: Add a couple trivial abs optimizations") Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3786> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3786>
* iris: fix aux buf map failure in 32bits app on AndroidTapani Pälli2020-02-131-8/+9
| | | | | | | | | Cc: [email protected] Reported-by: Zhifang Long <[email protected]> Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3784> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3784>
* radv: remove unused RADV_HASH_SHADER_IS_GEOM_COPY_SHADERSamuel Pitoiset2020-02-131-6/+5
| | | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3789> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3789>
* radv: remove RADV_DEBUG=nosisched and RADV_PERFTEST=sischedSamuel Pitoiset2020-02-136-47/+32
| | | | | | | | They are no longer useful. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3789>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-15 01:18:28 +0000