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* anv: Add vma_heap allocators in anv_deviceScott D Phillips2018-05-312-0/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These will be used to assign virtual addresses to soft pinned buffers in a later patch. Two allocators are added for separate 'low' and 'high' virtual memory areas. Another alternative would have been to add a double-sided allocator, which wasn't done here just because it didn't appear to give any code complexity advantages. v2 (Scott Phillips): - rename has_exec_softpin to use_softpin (Jason) - Only remove bottom one page and top 4 GiB from virt (Jason) - refer to comment in anv_allocator about state address + size overflowing 48 bits (Jason) - Mention hi/lo allocators vs double-sided allocator in commit message (Chris) - assign state pool memory ranges statically (Jason) v3 (Jason Ekstrand): - Use (LOW|HIGH)_HEAP_(MIN|MAX)_ADDRESS rather than (1 << 31) for determining which heap to use in anv_vma_free - Only return de-canonicalized addresses to the heap Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel/common: Add an address de-canonicalization helperJason Ekstrand2018-05-311-0/+12
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* util: Add a randomized test for the virtual memory allocatorScott D Phillips2018-05-316-1/+316
| | | | | | | | | | | | | | | | | The test pseudo-randomly makes allocations and deallocations with the virtual memory allocator and checks that the results are consistent. Specifically, we test that: * no result from the allocator overlaps an already allocated range * allocated memory fulfills the stated alignment requirement * a failed result from the allocator could not have been fulfilled * memory freed to the allocator can later be allocated again v2: - fix if() in test() to actually run fill() v3: - add c++11 build flag (Jason) - test the full 64-bit range (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* util: Add a virtual memory allocatorJason Ekstrand2018-05-314-1/+292
| | | | | | | | | | | | | | | | | | | | | | This is simple linear-walk first-fit allocator roughly based on the allocator in the radeon winsys code. This allocator has two primary functional differences: 1) It cleanly returns 0 on allocation failure 2) It allocates addresses top-down instead of bottom-up. The second one is needed for Intel because high addresses (with bit 47 set) need to be canonicalized in order to work properly. If we allocate bottom-up, then high addresses will be very rare (if they ever happen). We'd rather always have high addresses so that the canonicalization code gets better testing. v2: - [scott-ph] remove _heap_validate() if NDEBUG is defined (Jordan) Reviewed-by: Scott D Phillips <[email protected]> Tested-by: Scott D Phillips <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radv: Add startup debug option.Bas Nieuwenhuizen2018-05-314-2/+50
| | | | | | | | | | | | | | | | This adds a RADV_DEBUG=startup option to dump more info about instance creation and device enumeration. A common question end users have is why the direver is not loading for them, and this has two common reasons: 1) They did not install the driver. 2) AMDGPU is not used for the card in the kernel. This adds some info messages so we can easily get a some useful output from end users. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Add option to print errors even in optimized builds.Bas Nieuwenhuizen2018-05-3114-96/+108
| | | | | | | | | | | Errors are not that common of a case so we can eat a slight perf hit in having to call a function and do a runtime check. In turn this makes debugging random errors happening for end users easier, because they don't have to have a debug build on hand. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Make the sem_info allocate/free functions static.Bas Nieuwenhuizen2018-05-312-15/+9
| | | | | | | They are only used in 1 file. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nir: optimize iand(ieq(a, 0), ieq(b, 0)) to ieq(ior(a, b), 0)Samuel Pitoiset2018-05-311-0/+2
| | | | | | | | | | | | | | Totals from affected shaders: SGPRS: 80 -> 80 (0.00 %) VGPRS: 48 -> 48 (0.00 %) Code Size: 2120 -> 2096 (-1.13 %) bytes Max Waves: 16 -> 16 (0.00 %) Only two Rise of Tomb Raider shaders are affected on my side. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: don't call Driver.TexEnv with invalid argumentsTapani Pälli2018-05-311-20/+34
| | | | | | | | | | Patch skips useless and possibly dangerous calls down to the driver in case invalid arguments were given. I noticed this would be happening with demo of Darwinia game. AFAIK this does not fix anything but makes this path safer and more like how other API functions are implemented. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* v3d: Fix automake linking error.Vinson Lee2018-05-301-1/+3
| | | | | | | | | | | | | CXXLD gallium_dri.la ../../../../src/broadcom/.libs/libbroadcom.a(clif_dump.o): In function `clif_dump_packet': src/broadcom/clif/clif_dump.c:87: undefined reference to `v3d33_clif_dump_packet' src/broadcom/clif/clif_dump.c:85: undefined reference to `v3d41_clif_dump_packet' ../../../../src/broadcom/.libs/libbroadcom.a(clif_dump.o): In function `clif_process_worklist': src/broadcom/clif/clif_dump.c:140: undefined reference to `v3d41_clif_dump_gl_shader_state_record' src/broadcom/clif/clif_dump.c:144: undefined reference to `v3d33_clif_dump_gl_shader_state_record' Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* virgl: Update virgl_hw.hJakob Bornecrantz2018-05-301-0/+1
| | | | | | Reviewed-by: Gurchetan Singh <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* virgl: add ARB_transform_feedback_overflow_query supportDave Airlie2018-05-302-2/+4
| | | | | Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* virgl: add polygon offset clampDave Airlie2018-05-301-1/+2
| | | | | Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* virgl: add derivative control supportDave Airlie2018-05-301-1/+2
| | | | | Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* virgl: add ARB_conditional_render_inverted supportDave Airlie2018-05-301-1/+2
| | | | | Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* virgl: update caps bitset to latest version.Dave Airlie2018-05-301-0/+5
| | | | | | | | This makes this use all 32 bits, so future sets need to be defined in a new struct. Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* nir: add unsigned comparison simplificationsTimothy Arceri2018-05-301-0/+2
| | | | | | | This avoids loop unrolling regressions in Wolfenstein II on DXVK with an upcoming optimisation series from Samuel. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Only expose subgroup shuffles on VI+.Bas Nieuwenhuizen2018-05-301-2/+5
| | | | | | | | | The current implementation depends on bpermute, which is VI+. Fixes: f2c6a550611 "radv: enable subgroup capabilities" Reviewed-by: Daniel Schürmann <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: fix emitting descriptor pointers with LLVM < 7Samuel Pitoiset2018-05-301-2/+4
| | | | | | | | | | This was terribly wrong, I forced use of 32-bit pointers when emitting shader descriptor pointers. This fixes GPU hangs with LLVM 5&6 because 32-bit pointers are only supported with LLVM 7. Fixes: 88d1ed0f81 ("radv: emit shader descriptor pointers consecutively") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nv30: add a couple of missed shader capsIlia Mirkin2018-05-301-0/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv30: ensure that displayable formats are marked accordinglyIlia Mirkin2018-05-301-4/+6
| | | | | | Fixes: f7604d8af52 ("st/dri: only expose config formats that are display targets") Cc: "18.1" <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]>
* mesa: expose ARB_tessellation_shader in the compatibility profileMarek Olšák2018-05-293-3/+6
| | | | | | | Gallium drivers don't expose this yet due to: "st/mesa: use PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY" Reviewed-by: Timothy Arceri <[email protected]>
* mesa: expose AMD_vertex_shader_layer in the compatibility profileMarek Olšák2018-05-292-2/+3
| | | | | | | | | | This requires layered FBOs from GL 3.2. Gallium drivers don't expose this yet due to: "st/mesa: use PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY" Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: expose ARB_gpu_shader5 in the compatibility profileMarek Olšák2018-05-292-3/+5
| | | | | | | Gallium drivers don't expose this yet due to: "st/mesa: use PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY" Reviewed-by: Timothy Arceri <[email protected]>
* st/mesa: use PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITYMarek Olšák2018-05-291-10/+15
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* gallium: add PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITYMarek Olšák2018-05-2918-0/+37
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: update fixed-func state constants for TCS, TES, GSMarek Olšák2018-05-291-28/+36
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: print Compatibility Profile in the version stringMarek Olšák2018-05-291-1/+3
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* glsl: parse #version XXX compatibilityMarek Olšák2018-05-291-4/+8
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* st/mesa: fix assertion failures with GL_UNSIGNED_INT64_ARB (v2)Marek Olšák2018-05-291-1/+2
| | | | | | | | Bindless texture handles can be passed via vertex attribs using this type. They use the double codepath, so don't use st_pipe_vertex_format. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: handle GL_UNSIGNED_INT64_ARB properly (v2)Marek Olšák2018-05-292-1/+3
| | | | | | | | Bindless texture handles can be passed via vertex attribs using this type. This fixes a bunch of bindless piglit tests on radeonsi. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: add display list support for glPatchParameter{i,fv}()Timothy Arceri2018-05-301-0/+78
| | | | | | This is required for tessellation shader Compat profile support. Reviewed-by: Marek Olšák <[email protected]>
* glx/drisw: make the shm/non-shm loader extensions separately.Dave Airlie2018-05-301-8/+24
| | | | | | | | I disliked removing the const here, function tables are meant to be const just to avoid having to think about them, make a second table for the shm vs non-shm paths to use. Reviewed-by: Adam Jackson <[email protected]>
* drisw/glx: implement getImageShmMarc-André Lureau2018-05-301-1/+30
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* drisw: use getImageShm() if availableMarc-André Lureau2018-05-301-1/+22
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* drisw: learn to query shmid handle typeMarc-André Lureau2018-05-304-3/+12
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* drisw/glx: use XShm if possibleMarc-André Lureau2018-05-302-24/+144
| | | | | | | | | | | | | | Implements putImageShm from DRIswrastLoaderExtension. If XShm extension is not available, or fails, it will fallback on regular XPutImage(). Tested on Linux only with 16bpp and 32bpp visual. (airlied: tested on 24bpp as well) Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* drisw: use shared memory when possibleMarc-André Lureau2018-05-301-12/+60
| | | | | | | | If drisw_loader_funcs implements put_image_shm, allocates display target data with shared memory and display with put_image_shm(). Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* drisw: use putImageShm if availableMarc-André Lureau2018-05-302-8/+32
| | | | | | | | If the DRIswrastLoaderExtension implements putImageShm, bind it to drisw_loader_funcs. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* dri: add putImageShm and getImageShm to swrastLoaderMarc-André Lureau2018-05-301-1/+19
| | | | | | | | | | | Add new API to put and get an image using shared memory. Instead of only passing the data pointer, 3 arguments are given: the shmid, the data offset and the shmaddr. Bump interface version. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* gallium/winsys: rename DRM_API_HANDLE_* to WINSYS_HANDLE_*Dave Airlie2018-05-3030-110/+110
| | | | | | | | | | | | This just renames this as we want to add an shm handle which isn't really drm related. Originally by: Marc-André Lureau <[email protected]> (airlied: I used this sed script instead) This was generated with: git grep -l 'DRM_API_' | xargs sed -i 's/DRM_API_/WINSYS_/g' Reviewed-by: Marek Olšák <[email protected]>
* gallium: move winsys handle to it's own file.Marc-André Lureau2018-05-302-47/+59
| | | | | | | This will be used in the drisw interface later, which isn't drm specific. Reviewed-by: Marek Olšák <[email protected]>
* intel/fs: Add explicit last_rt flag to fb writes orthogonal to eot.Francisco Jerez2018-05-294-5/+5
| | | | | | | | | | | | | | When using multiple RT write messages to the same RT such as for dual-source blending or all RT writes in SIMD32, we have to set the "Last Render Target Select" bit on all write messages that target the last RT but only set EOT on the last RT write in the shader. Special-casing for dual-source blend works today because that is the only case which requires multiple RT write messages per RT. When we start doing SIMD32, this will become much more common so we add a dedicated bit for it. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/fs: Replace the CINTERP opcode with a simple MOVFrancisco Jerez2018-05-295-12/+3
| | | | | | | | | | | | | The only reason it was it's own opcode was so that we could detect it and adjust the source register based on the payload setup. Now that we're using the ATTR file for FS inputs, there's no point in having a magic opcode for this. v2 (Jason Ekstrand): - Break the bit which removes the CINTERP opcode into its own patch Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/fs: Use the ATTR file for FS inputsFrancisco Jerez2018-05-294-22/+30
| | | | | | | | | | | | This replaces the special magic opcodes which implicitly read inputs with explicit use of the ATTR file. v2 (Jason Ekstrand): - Break into multiple patches - Change the units of the FS ATTR to be in logical scalars Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/fs: Rename a local variable so it doesn't shadow component()Francisco Jerez2018-05-291-4/+4
| | | | | | | | | v2 (Jason Ekstrand): - Break the refactor into its own patch Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/eu: Remove brw_codegen::compressed_stack.Francisco Jerez2018-05-291-1/+0
| | | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/fs: Use groups for SIMD16 LINTERP on gen11+Jason Ekstrand2018-05-291-4/+5
| | | | | | | | | | | This is better than compression control because it naturally extends to SIMD32. v2: - Push/pop instruction state around adjusted codegen (Ken) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/fs: Assert that the gen4-6 plane restrictions are followedJason Ekstrand2018-05-291-2/+8
| | | | | | | The fall-back does not work correctly in SIMD16 mode and the register allocator should ensure that we never hit this case anyway. Reviewed-by: Matt Turner <[email protected]>
* travis: Add clover llvm-6.0 buildJan Vesely2018-05-291-0/+33
| | | | | | v2: Don't force build using gcc-4.8 Signed-off-by: Jan Vesely <[email protected]> Reviewed-By: Aaron Watry <[email protected]>
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