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* pan/mdg: Set lower_flrp16Alyssa Rosenzweig2020-04-291-0/+1
* pan/mdg: Remove old hackAlyssa Rosenzweig2020-04-291-3/+0
* pan/mdg: Remove goofy 16-bit commentAlyssa Rosenzweig2020-04-291-8/+0
* pan/mdg: Don't break SSAAlyssa Rosenzweig2020-04-291-7/+2
* pan/mdg: SSA_FIXED_MINIMUM already covered by PAN_IS_REGAlyssa Rosenzweig2020-04-292-3/+1
* pan/mdg: Use PAN_IS_REGAlyssa Rosenzweig2020-04-296-21/+17
* pan/mdg: Remove nir_alu_src_indexAlyssa Rosenzweig2020-04-293-10/+4
* pan/bi: Use common IR indicesAlyssa Rosenzweig2020-04-296-57/+24
* panfrost: Move Bifrost IR indexing to commonAlyssa Rosenzweig2020-04-291-0/+32
* panfrost: Fix BO reference countingAlyssa Rosenzweig2020-04-291-2/+2
* ac: enable displayable DCC on Navi12 & Navi14Marek Olšák2020-04-291-4/+7
* ac/surface: validate that DCC is enabled correctly on gfx9+Marek Olšák2020-04-291-0/+69
* ac/surface: add code for gfx10 displayable DCCMarek Olšák2020-04-296-26/+88
* ac/surface: move non-displayable DCC to the end of the bufferMarek Olšák2020-04-291-3/+6
* ac/surface: don't compute DCC if it's unsupported by DCN on gfx9+Marek Olšák2020-04-292-21/+30
* ac/surface: match get_display_flag() with expectations for is_displayableMarek Olšák2020-04-291-1/+7
* ac/surface: replace RADEON_SURF_OPTIMIZE_FOR_SPACE with !FORCE_SWIZZLE_MODEMarek Olšák2020-04-295-10/+8
* ac/surface: remove RADEON_SURF_TC_COMPATIBLE_HTILE and assume it's always setMarek Olšák2020-04-294-23/+30
* ac/surface: rename micro tile mode enums like gfx10 uses themMarek Olšák2020-04-294-15/+17
* winsys/svga: Optionally avoid caching buffer mapsThomas Hellstrom2020-04-294-12/+22
* gallium/pipebuffer: Use persistent maps for slabsThomas Hellstrom2020-04-293-4/+14
* radv: Use smaller esgs_itemsize for ACO.Timur Kristóf2020-04-294-23/+30
* aco: Use new default driver locations.Timur Kristóf2020-04-291-107/+17
* radv: Use new linking helper to set default driver locations.Timur Kristóf2020-04-292-0/+58
* nir: Add new linking helper to set linked driver locations.Timur Kristóf2020-04-292-0/+108
* aco: Set config->lds_size when TES or VS is running on HW ESGS.Timur Kristóf2020-04-291-0/+1
* aco: Calculate workgroup size of legacy GS.Timur Kristóf2020-04-291-1/+5
* aco: Remember VS/TCS output driver locations.Timur Kristóf2020-04-292-10/+18
* aco: Use context variables instead of calculating TCS inputs/outputs.Timur Kristóf2020-04-292-11/+7
* radv: Refactor calculate_tess_lds_size and get_tcs_num_patches.Timur Kristóf2020-04-293-21/+25
* aco: consider blocks unreachable if they are in the logical cfgRhys Perry2020-04-296-9/+2
* egl/wayland: Fix zwp_linux_dmabuf usageChristopher James Halse Rogers2020-04-291-12/+20
* iris/bufmgr: Check if iris_bo_gem_mmap failedDanylo Piliaiev2020-04-291-0/+8
* anv: remove assert from GetImageMemoryRequirements[2]Tapani Pälli2020-04-291-12/+0
* gitlab-ci: add a list of expected failures for FIJI with ACOSamuel Pitoiset2020-04-291-0/+36
* radv: advertise VK_EXT_robustness2Samuel Pitoiset2020-04-293-1/+17
* radv: handle NULL vertex bindingsSamuel Pitoiset2020-04-291-4/+7
* radv: handle NULL descriptorsSamuel Pitoiset2020-04-291-2/+24
* aco: fix adjusting the sample index with FMASK if value is negativeSamuel Pitoiset2020-04-291-2/+6
* aco: fix nir_texop_texture_samples with NULL descriptorsSamuel Pitoiset2020-04-291-2/+12
* ac/llvm: fix nir_texop_texture_samples with NULL descriptorsSamuel Pitoiset2020-04-291-1/+22
* intel/fs: Only stall after sending all memory fence messagesCaio Marcelo de Oliveira Filho2020-04-291-19/+16
* intel/fs,vec4: Pull stall logic for memory fences up into the IRCaio Marcelo de Oliveira Filho2020-04-297-109/+118
* intel/fs: Allow FS_OPCODE_SCHEDULING_FENCE stall on registersCaio Marcelo de Oliveira Filho2020-04-292-2/+30
* radv: Expose 4G element texel buffers.Bas Nieuwenhuizen2020-04-291-1/+1
* iris: Fix downcast of bound_vertex_buffers from uint64_t to intKenneth Graunke2020-04-291-1/+1
* intel/ir: Remove scheduling-based cycle count estimates.Francisco Jerez2020-04-283-26/+1
* intel/ir: Pass block cycle count information explicitly to disassembler.Francisco Jerez2020-04-285-6/+11
* intel/ir: Use brw::performance object instead of CFG cycle counts for codegen...Francisco Jerez2020-04-289-22/+45
* intel/fs: Add INTEL_DEBUG=no32 debugging flag.Francisco Jerez2020-04-283-2/+5
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