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* util: fix NORETURN for msvc, add HAVE_FUNC_ATTRIBUTE_NORETURN to c99_compat.hRoland Scheidegger2018-01-122-4/+9
* radv: don't emit unneeded vertex state.Dave Airlie2018-01-122-8/+49
* radv: trim buffer load result (fixes dota2)Dave Airlie2018-01-121-1/+1
* meson: add variable for including include/GL/internalDylan Baker2018-01-113-10/+5
* meson: define inc_gbm as empty if not otherwise assignedDylan Baker2018-01-111-0/+2
* meson: move libsensors dependency to libgalliumDylan Baker2018-01-118-13/+7
* meson: Use dependencies for nirDylan Baker2018-01-1118-50/+72
* meson: don't use intermediate variables that are immediately discardedDylan Baker2018-01-115-14/+7
* meson: Use consistent style for testsDylan Baker2018-01-1120-151/+199
* meson: Use include variablesDylan Baker2018-01-111-1/+1
* meson: Use consistent styleDylan Baker2018-01-1117-85/+148
* i965: Use UD types for gl_SampleID setupJason Ekstrand2018-01-111-3/+3
* i965/fs: Use UW types when using V immediatesJason Ekstrand2018-01-112-5/+5
* ac/nir: fix translation of nir_op_fsign for doublesTimothy Arceri2018-01-121-7/+19
* ac: add f64_0 to the llvm build contextTimothy Arceri2018-01-122-0/+2
* ac/nir: fix translation of nir_op_frcp for doublesTimothy Arceri2018-01-121-1/+2
* ac/nir: fix translation of nir_op_frsq for doublesTimothy Arceri2018-01-121-1/+2
* ac: add f64_1 to the llvm build contextTimothy Arceri2018-01-122-0/+2
* radv: reset semaphores & fences on sync_file export.Bas Nieuwenhuizen2018-01-111-0/+16
* intel: Add more Coffee Lake PCI IDsAnuj Phogat2018-01-111-1/+9
* Revert "Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+""Matt Turner2018-01-111-4/+8
* i965/fs: Add/use functions to convert to 3src_align1 vstride/hstrideMatt Turner2018-01-111-28/+41
* anv: Make sure state on primary is correct after CmdExecuteCommandsAlex Smith2018-01-111-0/+9
* svga: simplify failure code in emit_rss_vgpu9()Brian Paul2018-01-111-17/+12
* svga: remove unused fail parameter to EMIT_RS(), EMIT_RS_FLOAT()Brian Paul2018-01-111-57/+57
* svga: add assertion in svga_queue_rs()Brian Paul2018-01-111-0/+1
* svga: whitespace/formatting fixes in svga_state_rss.cBrian Paul2018-01-111-79/+75
* anv: Import mako templates only during execution of anv_extensionsAndres Gomez2018-01-111-5/+5
* glsl: cleanup shader_cache header guardTapani Pälli2018-01-111-3/+3
* anv: fix maxDescriptorSet* limitsSamuel Iglesias Gonsálvez2018-01-111-5/+5
* ac: add load_patch_vertices_in() to the abiTimothy Arceri2018-01-113-7/+26
* ac/nir: Sanitize location_frac for local variables.Bas Nieuwenhuizen2018-01-111-0/+1
* tgsi: include struct definitions for tgsi_build declarationsRob Herring2018-01-101-5/+1
* swr: Handle indirect indices in GSGeorge Kyriazis2018-01-101-8/+39
* amd/common: use ac_build_buffer_load() for emitting UBO loadsSamuel Pitoiset2018-01-101-14/+3
* amd/common: import get_{load,store}_intr_attribs() from RadeonSISamuel Pitoiset2018-01-103-31/+25
* dri_util: remove ALLOW_RGB10_CONFIGS option (v2)Marek Olšák2018-01-102-5/+2
* swr/rast: switch win32 jit format to COFFTim Rowley2018-01-101-2/+2
* swr/rast: don't use 32-bit gathers for elements < 32-bits in sizeTim Rowley2018-01-101-1/+60
* swr/rast: autogenerate named structs instead of literal structsTim Rowley2018-01-101-8/+15
* swr/rast: SIMD16 fetch shader jitter cleanupTim Rowley2018-01-101-720/+368
* swr/rast: shuffle header files for msvc pre-compiled header usageTim Rowley2018-01-1010-88/+143
* swr/rast: SIMD16 builder - cleanup naming (simd2 -> simd16)Tim Rowley2018-01-105-233/+239
* glsl/linker: Safely generate mask of possible locationsIan Romanick2018-01-101-4/+5
* glsl/linker: Mark no locations as invalid instead of marking all locationsIan Romanick2018-01-101-1/+1
* glsl: Don't handle visit_stop in several ::accept methodsIan Romanick2018-01-101-3/+6
* glsl: Remove unnecessary assignments to typeIan Romanick2018-01-101-4/+0
* nir: Silence unused parameter warningsIan Romanick2018-01-101-2/+2
* radv: Remove some typos.Bas Nieuwenhuizen2018-01-102-4/+4
* radv: Implement VK_EXT_discard_rectangles.Bas Nieuwenhuizen2018-01-105-6/+110
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