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* etnaviv: Only use renderonly_get_handle for GEM handles.Eric Anholt2017-06-152-1/+3
| | | | | | | | | | | | Note that for requests for Prime FDs or flink names, we return handles to the etanviv BO, not the scanout BO. This is at least better than previous behavior of returning GEM handles for a request for an FD or flink name. And add an assert that renderonly_get_handle is only used for getting the GEM handle. Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* android: r600/eg: add support for tracing IBs after a hang.Mauro Rossi2017-06-151-0/+10
| | | | | | | The rules to generate egd_tables.h are added in Android makefile Fixes: f42fb00 "r600/eg: add support for tracing IBs after a hang." Reviewed-by: Emil Velikov <[email protected]>
* svga: fix git_sha1.h include path in Android.mk (v3)Mauro Rossi2017-06-156-14/+66
| | | | | | | | | | | | | | | | | | | | Adds libmesa_git_sha1 static (dummy) library to generate git_sha1.h with some polishing to header dependency on .git/HEAD and scripted rules. The now redundant generation rules are removed from Android.gen.mk libmesa_git_sha1 whole static depedency is added to libmesa_pipe_svga, libmesa_dricore and libmesa_st_mesa modules Fixes the following building error: external/mesa/src/gallium/drivers/svga/svga_screen.c:26:10: fatal error: 'git_sha1.h' file not found ^ 1 error generated. Fixes: 1ce3a27 ("svga: Add the ability to log messages to vmware.log on the host.") Reviewed-by: Emil Velikov <[email protected]>
* bin/get-fixes-pick-list.sh: better identify multiple "fixes:" tagsAndres Gomez2017-06-151-4/+7
| | | | | | | | | | | | | | | | | | | | | | | We were not considering as multiple fixes lines with: Fixes: $sha_1, Fixes: $sha_2 Now, we split the lines so we will consider them individually, as in: Fixes: $sha_1, Fixes: $sha_2 Additionally, we try to get the SHA from split lines so: Fixes: $sha_1 Will be considered as: Fixes: $sha_1 v2: - Treat empty spaces earlier in fix lines (Emil) - Fold 2 lines into one to gather fix commit ids (Emil) Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* bin/get-fixes-pick-list.sh: parse just the commit messageAndres Gomez2017-06-151-2/+2
| | | | | | | | | | We were parsing the whole diff, although the candidates were identified only by the commit message. Now, we only use the commit message for parsing. Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* gallium/radeon: fix initialization of new resource bindless fieldsSamuel Pitoiset2017-06-151-0/+2
| | | | | | | r600_resource objects are not calloc'd. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gbm: implement FD import with modifierLucas Stach2017-06-151-0/+54
| | | | | | | | | | This implements a way to import FDs with modifiers on plain GBM devices, without the need to go through EGL. This is mostly to the benefit of gbm_gralloc, which can keep its dependencies low. Signed-off-by: Lucas Stach <[email protected]> Tested-by: Robert Foss <[email protected]> Reviewed-by: Daniel Stone <[email protected]>
* gbm: add API to to import FD with modifierLucas Stach2017-06-151-0/+12
| | | | | | | | | This allows to import an FD with an explicit modifier passed through userspace protocols. Signed-off-by: Lucas Stach <[email protected]> Tested-by: Robert Foss <[email protected]> Reviewed-by: Daniel Stone <[email protected]>
* i965: gen4_blorp_exec.h to the sources listEmil Velikov2017-06-152-1/+1
| | | | | | | | We tend to use the sources, as opposed to EXTRA_DIST to include the headers. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Juan A. Suarez Romero <[email protected]>
* gallium/util: Break recursion in pipe_resource_referenceMichel Dänzer2017-06-151-2/+8
| | | | | | | | | | | | | | | | | | | | It calling itself recursively prevented it from being inlined, resulting in a copy being generated in every compilation unit referencing it. This bloated the text segment of the Gallium mega-driver *_dri.so by ~4%, and might also have impacted performance. Fixes: ecd6fce2611e ("mesa/st: support lowering multi-planar YUV") v2: * Add comment above pipe_resource_next_reference [Samuel Pitoiset] v3: * Use loop to unreference the full chain of resources referenced via the next members [Timothy Arceri] v4: * Stop chasing ->next chain at the first sub-resource which isn't destroyed [Nicolai Hähnle] Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: fix 'make check' by moving bindless functions at the right placeSamuel Pitoiset2017-06-151-18/+18
| | | | | | | | | Fixes: 5f249b9f05e ("mapi: add GL_ARB_bindless_texture entry points") Reported-by: Mark Janes <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Aaron Watry <[email protected]> Tested-by: Michel Dänzer <[email protected]>
* i965/miptree: Use the new simple alloc_tiled for CCS buffersJason Ekstrand2017-06-141-7/+2
| | | | | Reviewed-by: Plamena Manolova <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/bufmgr: Add a new, simpler, bo_alloc_tiledJason Ekstrand2017-06-142-0/+26
| | | | | | | | | | | | | ISL already has all of the complexity required to figure out the correct surface pitch and size taking tile alignment into account. When we get a surface out of ISL, the pitch and size are already correct and using brw_bo_alloc_tiled_2d doesn't actually gain us anything other than extra asserts we have to do in order to ensure that the bufmgr code and ISL agree. This new helper doesn't try to be smart but just allocates the BO you ask for and sets up the tiling. Reviewed-by: Plamena Manolova <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/bufmgr: Rename bo_alloc_tiled to bo_alloc_tiled_2dJason Ekstrand2017-06-144-44/+44
| | | | | Reviewed-by: Plamena Manolova <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use blorp for depth/stencil clears on gen6+Jason Ekstrand2017-06-143-0/+115
| | | | | Acked-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Set step_rate = 0 for interleaved vertex buffersJason Ekstrand2017-06-141-0/+1
| | | | | | | | | | | | | | | | | Before, we weren't setting step rate so we got whatever old value happened to be lying around. This can lead to some interesting rendering errors. In particular, if you run the OpenGL ES CTS with dEQP-GLES3.functional.instanced.types.mat2x4 immediately followed by one of the dEQP-GLES3.functional.transform_feedback.* tests, the transform feedback test gets stale instancing data from the other test and fails. The only thing that is causing this to not be a problem today is that we use meta for clears and meta is setting up vertex buffers via the VBO or non-interleaved path and setting step_rate to 0 for us. When blorp depth/stencil clears are enabled, meta is no longer sitting between the two tests and the stale data starts causing noticeable problems. Cc: "17.1" <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Disable the interleaved vertex optimization when instancingJason Ekstrand2017-06-141-5/+6
| | | | | | | | Instance divisor is a property of the vertex buffer and not the vertex element so if we ever see anything other than 0, bail. Cc: "17.1" <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel/blorp: Work around Sandy Bridge occlusion query issueJason Ekstrand2017-06-141-0/+10
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965/blorp: Set no_depth_or_stencil correctlyJason Ekstrand2017-06-141-1/+2
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Remove some unneeded fields from brw_contextJason Ekstrand2017-06-141-12/+0
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Remove some of the remnants of metaJason Ekstrand2017-06-143-3/+2
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel/isl: Properly set SeparateStencilBufferEnable on gen5-6Jason Ekstrand2017-06-141-3/+10
| | | | | | | On gen5-6, SeparateStencilBufferEnable and HierarchicalDepthBufferEnable come hand in hand and we have to set either both or neither. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965/miptree: Choose the stencil layout in miptree_create_layoutJason Ekstrand2017-06-141-2/+4
| | | | | | | This ensures that we get the correct layout for all stencil buffers, not just those which are created as separate stencil for a depth buffer. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* mesa: Add a BUFFER_BITS mask for depth+stencilJason Ekstrand2017-06-141-0/+3
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965/blorp: Set aux_usage to NONE for miplevels without HiZJason Ekstrand2017-06-141-0/+6
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* radeon/winsys: Limit max allocation size to 70% of VRAMAaron Watry2017-06-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The CL CTS queries the max allocation size, and then attempts to allocate buffers of that size. If not enough contiguous RAM/VRAM is available, this causes errors in the radeon kernel module due to inability to allocate the required memory. It's a bit of a hack, but experimentally on my system, I can use ~3/4 of the card's VRAM for a single global/constant buffer allocation given current GUI/compositor use. For a 1GB Pitcairn (HD7850) this gets me from the reported clinfo values of: Global memory size 2143076352 (1.996GiB) Max memory allocation 1500153446 (1.397GiB) Max constant buffer size 1500153446 (1.397GiB) To: Global memory size 2143076352 (1.996GiB) Max memory allocation 751619276 (716MiB) Max constant buffer size 751619276 (716MiB) Fixes: OpenCL CTS test/conformance/api/min_max_mem_alloc_size, OpenCL CTS test/conformance/api/min_max_constant_buffer_size Signed-off-by: Aaron Watry <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: Use a line end cap width of 0.5 unless smooth lines enabled.Kenneth Graunke2017-06-141-2/+3
| | | | | | | | This updates the Gen4-5 code to use a line end cap width of 0.5 for non-smooth lines, and 1.0 for smooth lines - which is what we do on Gen6+. Reviewed-by: Rafael Antognolli <[email protected]>
* i965: Use brw_get_line_width() in Gen4-5 SF_STATE code.Kenneth Graunke2017-06-141-4/+2
| | | | | | | | | | | | | | | | | This unifies the Gen4-5 and Gen6+ line width calculations. I believe it also fixes a bug - we weren't rounding the line width to the nearest integer. The GL 4.5 (and GL 2.1) specs "Wide Lines" section says: "The actual width of non-antialiased lines is determined by rounding the supplied width to the nearest integer, then clamping it to the implementation-dependent maximum non-antialiased line width." We don't need to care about _NEW_MULTISAMPLE here because multisampling doesn't exist on Gen4-5, so the state shouldn't change. Reviewed-by: Rafael Antognolli <[email protected]>
* genxml: Fix Gen4-5 SF_STATE "Line Width" fixed point type.Kenneth Graunke2017-06-143-3/+3
| | | | | | It's a U3.1. It became a U3.7 on Sandybridge. Reviewed-by: Rafael Antognolli <[email protected]>
* i965: Stop using BRW_RASTRULE_LOWER_RIGHT on Gen4-5.Kenneth Graunke2017-06-141-27/+1
| | | | | | | | | | | | | | | | | | | This effectively reverts Robert Ellison's 2009 commit cc8afbd3862fedfe42e51c3774960d1c7078ec53. I'm not seeing any GL spec text indicating that UPPER won't work. On Gen6+, this bit moved to 3DSTATE_WM as a single bit, controlling UPPER_LEFT vs. UPPER_RIGHT. There is no way to request LOWER_RIGHT, so UPPER_RIGHT is the best you can do. In the G45 docs, it's marked as "Reserved" as well, but we just decided to use it anyway. This patch unifies the behavior between Gen4-5 and Gen6+. Note that this is separate from point sprite texcoord behavior. Reviewed-by: Rafael Antognolli <[email protected]>
* i965: When gl_PointSize is unwritten, default to 1.0 on Gen4-5.Kenneth Graunke2017-06-141-3/+3
| | | | | | | | | | | | | | | | Modern GL specifications say that the point size should be 1.0 when gl_PointSize is unwritten and the last enabled stage is a geometry or tessellation shader. If it's a vertex shader, though, both the GL specs and ES 3.0 spec say that it's undefined - so since Gen4-5 only support vertex shaders, there's no actual requirement to do this. Since there is a cost associated (an extra dirty bit, which may cause SF_STATE to be emitted more often), it may not be a good idea. The real benefit is that it makes all generations behave identically. And that seems somewhat nice... Reviewed-by: Rafael Antognolli <[email protected]>
* i965: Make Gen4-5 SF_STATE use the point size calculations from Gen6+.Kenneth Graunke2017-06-141-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Apparently, Nanhai made the Gen4-5 point size calculations round to the nearest integer in commit 8d5231a3582e4f2769ac0685cf0174e09750700e, "according to spec". When Eric first ported the driver to Sandybridge, he did not implement this rounding. In the GL 2.1 and 3.0 specs "Basic Point Rasterization" section, it does say "If antialiasing and point sprites are disabled, the actual width is determined by rounding the supplied width to the nearest integer, then clamping it to the implementation-dependent maximum non-antialised point width." In contrast, GL 3.1 and later do not appear to contain this rounding. It might be reasonable to round, given that we only implement GL 2.1. Of course, if we were to do that, we should actually implement the AA vs. non-AA distinction. Brian added an XXX comment reminding us to fix this 10 years ago, but it never happened. I think a better plan is to follow the newer, unrounded behavior. This is what we do on Gen6+ and it passes all the relevant conformance tests. Reviewed-by: Rafael Antognolli <[email protected]>
* i965: Do an end-of-pipe sync after flushesJason Ekstrand2017-06-141-3/+3
| | | | | | | | According to the docs, a simple CS stall is insufficient to ensure that the memory from the flush is visible and an end-of-pipe sync is needed. Cc: "17.1" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Do an end-of-pipe sync around CCS opsJason Ekstrand2017-06-141-12/+4
| | | | | Cc: "17.1" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Do an end-of-pipe sync prior to STATE_BASE_ADDRESSJason Ekstrand2017-06-141-6/+12
| | | | | Cc: "17.1" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add an end-of-pipe sync helperTopi Pohjolainen2017-06-142-1/+100
| | | | | | | | | | | v2 (Jason Ekstrand): - Take a flags parameter to control the flushes - Refactoring Cc: "17.1" <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Unify the two emit_pipe_control functionsJason Ekstrand2017-06-141-73/+64
| | | | | | | | | | These two functions contain almost identical logic except for one SNB workaround required for render target cache flushes. They may as well call into the same code so we only have to handle the work-arounds in one place. Cc: "17.1" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Take a uint64_t immediate in emit_pipe_control_writeJason Ekstrand2017-06-144-17/+14
| | | | | | | | It's a 64-bit value. Splitting it up just makes the function arguments awkward. Cc: "17.1" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Flush around state base addressJason Ekstrand2017-06-142-1/+33
| | | | | Cc: "17.1" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Print "force dual color blending" in FS recompile debug output.Kenneth Graunke2017-06-141-0/+3
| | | | | | | | I forgot to add this when introducing the new key field. It doesn't happen often - just with the Unigine workarounds. But we may as well have it, so we get an accurate picture of why recompiles happen. Reviewed-by: Alejandro Piñeiro <[email protected]>
* Fix khrplatform.h not installed if EGL is disabled.Eric Le Bihan2017-06-142-3/+3
| | | | | | | | | | | KHR/khrplatform.h is required by the EGL, GLES and VG headers, but is only installed if Mesa3d is compiled with EGL support. This patch installs this header file unconditionally. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77240 Signed-off-by: Eric Le Bihan <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i915: Fix wpos_tex vs. -1 comparisonVille Syrjälä2017-06-143-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | wpos_tex used to be a GLuint so assigning -1 to it and later comparing with -1 worked correctly, but commit c349031c27b7 ("i915: Fix texcoord vs. varying collision in fragment programs") changed wpos_tex to uint8_t and hence broke the comparison. To fix this define a more explicit invalid value for wpos_tex. gcc warns us: i915_fragprog.c:1255:57: warning: comparison is always true due to limited range of data type [-Wtype-limits] if (inputsRead & VARYING_BITS_TEX_ANY || p->wpos_tex != -1) { ^ And clang says: i915_fragprog.c:1255:57: warning: comparison of constant -1 with expression of type 'uint8_t' (aka 'unsigned char') is always true [-Wtautological-constant-out-of-range-compare] if (inputsRead & VARYING_BITS_TEX_ANY || p->wpos_tex != -1) { ~~~~~~~~~~~ ^ ~~ Cc: Chih-Wei Huang <[email protected]> Cc: Eric Anholt <[email protected]> Cc: Ian Romanick <[email protected]> Cc: [email protected] Fixes: c349031c27b7 ("i915: Fix texcoord vs. varying collision in fragment programs") Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* tgsi/scan: add missing 'static' to tgsi_is_bindless_image_file()Samuel Pitoiset2017-06-141-1/+1
| | | | | | | | This should fix compilation errors in some situations. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101418 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* configure.ac: Reduce zlib requirement from 1.2.8 to 1.2.3.Chuck Atkins2017-06-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Testing with zlib versions 1.2.{3,4,5,6,7,8} showed no difference in functionality, correctness, or zlib API usage and 1.2.3 is the oldest version available in still actively deployed production Linux distributions (RHEL/CentOS 6 and SuSE 11). Build 17.1.1 against the system supplied zlib-devel packages for 1.2.3 in EL6 and 1.2.7 on EL7. I then swapped out the zlib version at runtime via LD_LIBRARY_PATH with ones build from the release tarballs from zlib.net Testwise - I ran the piglit shader profile with --quick addded to the tests since I figured that would exercise the shader cache, which would in turn use zlib. Signed-off-by: Chuck Atkins <[email protected]> Cc: 17.1 <[email protected]> Cc: Timothy Arceri <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> [Emil Velikov: add hunk about version/piglit testing] Acked-by: Emil Velikov <[email protected]>
* radeonsi: enable ARB_bindless_textureSamuel Pitoiset2017-06-143-2/+5
| | | | | | | This has only been tested on RX480. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add support for loading bindless imagesSamuel Pitoiset2017-06-141-7/+21
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add support for loading bindless samplersSamuel Pitoiset2017-06-141-3/+12
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: invalidate buffers which are made resident if neededSamuel Pitoiset2017-06-141-0/+34
| | | | | | | | When a buffer becomes resident, check if it has been invalidated, if so update the descriptor and the dirty flag. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: upload new descriptors when resident buffers are invalidatedSamuel Pitoiset2017-06-143-0/+152
| | | | | | | | | | | | | When texture buffers are invalidated the addr in the resident descriptor has to be updated but we can't create a new descriptor because the resident handle has to be the same. Instead, use the WRITE_DATA packet which allows to update memory directly but graphics/compute have to be idle in case the GPU is reading the descriptor. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: only decompress resident textures/images when usedSamuel Pitoiset2017-06-141-2/+11
| | | | | | | | When the current bound shaders don't use any bindless textures or images, it's useless to decompress the resident resources. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
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