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* configure.ac: Refuse to build with Sun C compiler.Jose Fonseca2015-12-021-0/+7
| | | | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=93189 Reviewed-by: Matt Turner <[email protected]> Tested-by: Vinson Lee <[email protected]> Acked-by: Alan Coopersmith <[email protected]>
* travis: Add a test build with scons.Eric Anholt2015-12-011-6/+15
| | | | | | | | | Since I just broke the scons build, I figured I'd make Travis test that I don't break it again in the future. The script runs the builds in parallel across VMs, so it still takes just 5 minutes to turn around results. Reviewed-by: Jose Fonseca <[email protected]>
* i965: Increase BRW_MAX_UBO to 14.Kenneth Graunke2015-12-011-1/+1
| | | | | | | | | | | | | | | | | | | | | The NVIDIA binary driver and Intel's closed source driver both expose 14 here, rather than the GL minimum of 12. Let's follow suit. Without this, Shadow of Mordor fails to render correctly and triggers OpenGL errors: Mesa: User error: GL_INVALID_VALUE in glBindBufferBase(index=68) Mesa: User error: GL_INVALID_VALUE in glUniformBlockBinding(block binding 68 >= 60) There are 5 stages (VS, TCS, TES, GS, FS), and 12 * 5 = 60 is too small. 14 * 5 = 70 will work just fine. Tapani believes this will also help Alien Isolation. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Acked-by: Tapani Pälli <[email protected]> Acked-by: Matt Turner <[email protected]>
* i965: Do dead-code elimination in a single pass.Matt Turner2015-12-013-29/+16
| | | | | | | | | | | | The first pass marked dead instructions as opcode = NOP, and a second pass deleted those instructions so that the live ranges used in the first pass wouldn't change. But since we're walking the instructions in reverse order, we can just do everything in one pass. The only thing we have to do is walk the blocks in reverse as well. Reviewed-by: Francisco Jerez <[email protected]>
* glsl: Rename safe_reverse -> reverse_safe.Matt Turner2015-12-013-7/+7
| | | | | | To match existing foreach_in_list_reverse_safe. Reviewed-by: Francisco Jerez <[email protected]>
* i965: Don't mark dead instructions' sources live.Matt Turner2015-12-012-0/+8
| | | | | | | Removes dead code from glsl-mat-from-int-ctor-03.shader_test. Reported-by: Juan A. Suarez Romero <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* r600: set mega fetch count to 16 for gs copy shaderDave Airlie2015-12-021-0/+1
| | | | | | Seems like MFC should be set for this shader. Signed-off-by: Dave Airlie <[email protected]>
* r600: increment ring index after emit vertex not before.Dave Airlie2015-12-021-18/+24
| | | | | | | The docs say we should send the emit after the ring writes, so lets do that and not have an ALU in between. Signed-off-by: Dave Airlie <[email protected]>
* r600: add alu + cf nop to copy shader on r600Dave Airlie2015-12-021-0/+10
| | | | | | | SB suggests we do this for r600, so lets do it, for the copy shader. Signed-off-by: Dave Airlie <[email protected]>
* r600: SMX returns CONTEXT_DONE early workaroundDave Airlie2015-12-022-1/+13
| | | | | | | | | streamout, gs rings bug on certain r600s, requires a wait idle before each surface sync. Reviewed-by: Marek Olšák <[email protected]> Cc: "10.6 11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: do SQ flush ES ring rolling workaroundDave Airlie2015-12-023-1/+8
| | | | | | | | | Need to insert a SQ_NON_EVENT when ever geometry shaders are enabled. Reviewed-by: Marek Olšák <[email protected]> Cc: "10.6 11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nv50,nvc0: allow to create resources other than buffersSamuel Pitoiset2015-12-015-4/+9
| | | | | | | | | | | | For the compute support, we might stick buffers as surfaces. This fixes an assertion when executing src/gallium/tests/trivial/compute. To avoid using these "restricted" surfaces as render targets, these assertions have been moved. Note that it's already handled for the framebuffer thing on nvc0. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* glapi: work-around MSVC 65K string length limitation for enums.cBrian Paul2015-12-011-3/+10
| | | | | | | | | | | String literals cannot exceed 65535 characters for MSVC. Instead of emiting a string, emit an array of characters. v2: fix indentation and add comment in the gl_enums.py file about this ugliness. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mapi: Fix enums.c build with other build systems.Eric Anholt2015-12-012-2/+2
| | | | | Tested with scons (by both myself and Mark Janes), Android is just copy and paste.
* travis: Initial import of travis instructions.Eric Anholt2015-12-011-0/+92
| | | | | | | | | | | | This just builds/installs our dependencies, and runs "make check". I'm interested in integrating more tests into it, but this seems like a pretty easy first start. If your personal branches of Mesa are on github, you can enable it on your account and the repository (see https://docs.travis-ci.com/user/for-beginners), then any pushes you do will get their HEAD commit tested, and any pull requests to your tree will get their merge commits tested.
* mesa: Drop the blacklisting of new GL enums.Eric Anholt2015-12-012-269/+2
| | | | | | | | | | | | | Now when people need new extensions, they can skip the entire enum-definition process, and we can stop reviewing new extension XML for its enum content. This also brings in a new enum that I wanted to use in enum_strings.cpp for testing the code generator. v2: Drop comment about disabled GL_1PASS_EXT test. Reviewed-by: Ian Romanick <[email protected]>
* mesa: Use a 32-bit offset for the enums.c string offset table.Eric Anholt2015-12-011-3/+1
| | | | | | | With GLES 3.1, GL 4.5, and many new vendor extensions about to get their enums added, we jump up to 85k of table. Reviewed-by: Ian Romanick <[email protected]>
* mesa: Prefer newer names to older ones among names present in core.Eric Anholt2015-12-011-17/+8
| | | | | | | | | | | | Sometimes GL likes to rename an old enum when it grows a more general purpose, and we should prefer the new name. Changes from this: GL_POINT/LINE_SIZE_* (1.1) -> GL_SMOOTH_POINT/LINE_SIZE_* (1.2) GL_FOG_COORDINATE_* (1.4) -> GL_FOG_COORD_* (1.5) GL_SOURCE[012]_RGB/ALPHA (1.3) -> GL_SRC0_RGB (1.5) GL_COPY_READ/WRITE_BUFFER (3.1) -> GL_COPY_READ_BUFFER_BINDING (4.2) Reviewed-by: Ian Romanick <[email protected]>
* mesa: Drop bitfield "enums" from the enum-to-string table.Eric Anholt2015-12-012-21/+23
| | | | | | | | | | | | | | Asking the table for bitfield names doesn't make any sense. For 0x10, do you want GL_GLYPH_HORIZONTAL_BEARING_ADVANCE_BIT_NV or GL_COLOR_BUFFER_BIT4_QCOM or GL_POLYGON_STIPPLE_BIT or GL_SHADER_GLOBAL_ACCESS_BARRIER_BIT_NV? Giving a useful answer would depend on a whole lot of context. This also fixes a bad enum table entry, where we chose GL_HINT_BIT instead of GL_ABGR_EXT for 0x8000, so we can now fix its entry in the enum_strings test. Reviewed-by: Ian Romanick <[email protected]>
* mesa: Switch to using the Khronos registry for generating enums.Eric Anholt2015-12-012-39/+370
| | | | | | | | | | | | | | | | | | | | | | | | I've used a bunch of python code to cut out new enums so that the two generated files can be diffed. I'll remove all that hardcoding in the following commits. All remaining differences between the generated code: - GL_TEXTURE_BUFFER_FORMAT didn't appear in GL3 when TBOs got merged to core, so it now gets an _ARB suffix instead. - Blacklisting can't keep EXT_sso's GL_ACTIVE_PROGRAM_EXT from becoming GL_ACTIVE_PROGRAM -- in our hash table, GL_ACTIVE_PROGRAM_EXT points at the GLES2 enum's value (aka GL_CURRENT_PROGRAM). By not blacklisting the core name, we get both enums translated. - GL_DRAW_FRAMEBUFFER_BINDING and GL_FRAMEBUFFER_BINDING both appeared in GL3 as synonyms, and the new code happens to choose GL_FRAMEBUFFER_BINDING instead. - GL_TEXTURE_COMPONENTS and GL_TEXTURE_INTERNAL_FORMAT both appear in 1.1, and the new code chooses GL_TEXTURE_INTERNAL_FORMAT instead (which seems better, to me) Reviewed-by: Ian Romanick <[email protected]>
* mesa: Remove the python mode bits from gl_enums.py.Eric Anholt2015-12-011-1/+0
| | | | | | | emacs whines at me every time I open the file about these unsafe variables, and the file was reformatted from 8 space to 4 space long ago. Reviewed-by: Ian Romanick <[email protected]>
* mesa: Drop apparently typoed GL_ALL_CLIENT_ATTRIB_BITS.Eric Anholt2015-12-012-4/+1
| | | | | | | | GL_ALL_ATTRIB_BITS is a thing, and GL_CLIENT_ALL_ATTRIB_BITS, but I don't see GL_ALL_CLIENT_ATTRIB_BITS in my grepping of khronos XML, GL extension specs, GL 1.1, GL 2.2, and GL 4.4. Reviewed-by: Brian Paul <[email protected]>
* mesa: Drop enums that had been removed in later revs of specs.Eric Anholt2015-12-013-6/+0
| | | | | | | | | Mesa hasn't been using these enums and the finalized specs don't reference them, so losing them from our generated enum-to-string code should be fine. Reduces diffs to generating from Khronos XML, which has these enums noted defined but commented out from any consumers. Reviewed-by: Ian Romanick <[email protected]>
* mesa: Fix a typo in AMD_performance_monitor enum.Eric Anholt2015-12-011-1/+1
| | | | Reviewed-by: Ian Romanick <[email protected]>
* mesa: Fix enum definition of CULL_VERTEX_EYE/OBJECT_POSITIONEric Anholt2015-12-011-2/+2
| | | | | | | In converting to using the Khronos XML, I found that our XML had these two swapped, and the text spec agreed. Reviewed-by: Ian Romanick <[email protected]>
* mesa: Add a copy of the Khronos gl.xml (SVN #31705).Eric Anholt2015-12-011-0/+45348
| | | | | | | | The intention here is to keep a pristine copy of the upstream gl.xml that can be updated at any time with a new version, and use that to generate Mesa code from instead of our private XML. Reviewed-by: Ian Romanick <[email protected]>
* mesa: Cut enum_strings.cpp test down to a few hand-chosen enums.Eric Anholt2015-12-011-1822/+36
| | | | | | | | | | | | | | | | The previous contents appeared to be the output of some form of code generation for all enums, with a few entries hand-edited to deal with oddness. The downside to this was that when an enum gets promoted from vendor to _EXT or _EXT to _ARB or _ARB to core, make check starts failing even when the commiter has done nothing wrong. Instead of black-box testing the code generation, pick a few enums that intentionally poke the interesting cases of code generation. People editing the code generator should be diffing the generated code anyway. This should catch when they fail to do so, without throwing false negatives when people update the GL XML. Reviewed-by: Ian Romanick <[email protected]>
* clover: Handle NULL devices returned by pipe_loader_probe() v2Tom Stellard2015-12-011-1/+2
| | | | | | | | | | | | | | | | | | | | | When probing for devices, clover will call pipe_loader_probe() twice. The first time to retrieve the number of devices, and then second time to retrieve the device structures. We currently assume that the return value of both calls will be the same, but this will not be the case if a device happens to disappear between the two calls. When a device disappears, the pipe_loader_probe() will add a NULL device to the device list, so we need to handle this. v2: - Keep range for loop Reviewed-by: Francisco Jerez <[email protected]> Acked-by: Emil Velikov <[email protected]> CC: <[email protected]>
* automake: fix some occurrences of hardcoded -ldl and -lpthreadJonathan Gray2015-12-012-2/+3
| | | | | | | | | Correct some occurrences of -ldl and -lpthread to use $(DLOPEN_LIBS) and $(PTHREAD_LIBS) respectively. Signed-off-by: Jonathan Gray <[email protected]> Cc: "11.0 11.1" <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* glsl/lower_ubo_reference: split struct copies into element copiesIago Toral Quiroga2015-12-011-2/+54
| | | | | | | | Improves register pressure, since otherwise we end up emitting loads for all the elements in the RHS and them emitting stores for all elements in the LHS. Reviewed-by: Jordan Justen <[email protected]>
* glsl/lower_ubo_reference: split array copies into element copiesIago Toral Quiroga2015-12-011-0/+67
| | | | | | | | | | | | | | | | | | | | | | | Improves register pressure, since otherwise we end up emitting loads for all the elements in the RHS and them emitting stores for all elements in the LHS. v2: - Mark progress properly. This also fixes some instances where the added nodes with individual element copies where not being lowered, which is expected behavior as explained in the documentation for visit_list_elements. - Only need to do this if the RHS is a buffer-backed variable. - We can also have arrays inside structs. A later patch will make it so we also split struct copies and end up with multiple ir_dereference_record assignments, so make sure that if any of these is an array copy, we also split it. Fixes the following piglit tests: tests/spec/arb_shader_storage_buffer_object/execution/large-field-copy.shader_test tests/spec/arb_shader_storage_buffer_object/linker/copy-large-array.shader_test Reviewed-by: Jordan Justen <[email protected]>
* st/va: also retrieve reference frames info for h264Julien Isorce2015-12-011-0/+52
| | | | | | | | Other hardwares than AMD require to parse: VAPictureParameterBufferH264.ReferenceFrames[16] Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: delay decoder creation until max_references is knownJulien Isorce2015-12-014-34/+68
| | | | | | | | | | | | | | | | | | In general max_references cannot be based on num_render_targets. This patch allows to allocate buffers with an accurate size. I.e. no more than necessary. For other codecs it is a fixed value 2. This is similar behaviour as vaapi/vdpau-driver. For now HEVC case defaults to num_render_targets as before. But it could also benefits this change by setting a more accurate max_references number in handlePictureParameterBuffer. Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* glsl/dead_builin_varyings: Fix gl_FragData array loweringIago Toral Quiroga2015-12-011-1/+1
| | | | | | | | | | | | | | | | | | | | | The current implementation looks for array dereferences on gl_FragData and immediately proceeds to lower them, however this is not enough because we can have array access on vector variables too, like in this code: out vec4 color; void main() { int i; for (i = 0; i < 4; i++) color[i] = 1.0; } Fix it by making sure that the actual variable being dereferenced is an array. Fixes a crash in: spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-ldexp-dvec4.shader_test Reviewed-by: Tapani Pälli <[email protected]>
* r600: workaround empty geom shader.Dave Airlie2015-12-011-0/+5
| | | | | | | | | | We need to emit at least one cut/emit in every geometry shader, the easiest workaround it to stick a single CUT at the top of each geom shader. Reviewed-by: Marek Olšák <[email protected]> Cc: "10.6 11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: rv670 use at least 16es/gs threadsDave Airlie2015-12-011-4/+5
| | | | | | | | This is specified in the docs for rv670 to work properly. Reviewed-by: Marek Olšák <[email protected]> Cc: "10.6 11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: geometry shader gsvs itemsize workaroundDave Airlie2015-12-011-0/+20
| | | | | | | | | | On some chips the GSVS itemsize needs to be aligned to a cacheline size. This only applies to some of the r600 family chips. Reviewed-by: Marek Olšák <[email protected]> Cc: "10.6 11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glsl: don't sort varying in separate shader modeGregory Hainaut2015-12-011-6/+32
| | | | | | | | | | | | | | | This fixes an issue where the addition of the FLAT qualifier in varying_matches::record() can break the expected varying order. It also avoids a future issue with the relaxing of interpolation qualifier matching constraints in GLSL 4.50. V2: (by Timothy Arceri) * reworked comment slightly Signed-off-by: Gregory Hainaut <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* glsl: don't dead code remove SSO varyings marked as activeGregory Hainaut2015-12-011-0/+14
| | | | | | | | | | | | | | | | | GL_ARB_separate_shader_objects allow matching by name variable or block interface. Input varyings can't be removed because it is will impact the location assignment. This fixes the bug 79783 and likely any application that uses GL_ARB_separate_shader_objects extension. V2 (by Timothy Arceri): * simplify now that builtins are not set as always active Signed-off-by: Gregory Hainaut <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> https://bugs.freedesktop.org/show_bug.cgi?id=79783
* glsl: add always_active_io attribute to ir_variableGregory Hainaut2015-12-013-0/+82
| | | | | | | | | | | | | | | | | | | | | | The value will be set in separate-shader program when an input/output must remains active. e.g. when deadcode removal isn't allowed because it will create interface location/name-matching mismatch. v3: * Rename the attribute * Use ir_variable directly instead of ir_variable_refcount_visitor * Move the foreach IR code in the linker file v4: * Fix variable name in assert v5 (by Timothy Arceri): * Rename functions and reword comments * Don't set always active on builtins Signed-off-by: Gregory Hainaut <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* glsl: copy how_declared when lowering interface blocksTimothy Arceri2015-12-011-0/+1
| | | | | Cc: Gregory Hainaut <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* glsl: optimise inputs/outputs with explicit locationsTimothy Arceri2015-12-012-14/+74
| | | | | | | | | | | | | | | | | | | This change allows used defined inputs/outputs with explicit locations to be removed if they are detected to not be used between shaders at link time. To enable this we change the is_unmatched_generic_inout field to be flagged when we have a user defined varying. Previously explicit_location was assumed to be set only in builtins however SSO allows the user to set an explicit location. We then add a function to match explicit locations between shaders. V2: call match_explicit_outputs_to_inputs() after is_unmatched_generic_inout has been initialised. Cc: Gregory Hainaut <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* r600/shader: split address get out to a function.Dave Airlie2015-12-011-1/+6
| | | | | | | This will be used in the tess shaders. Reviewed-by: Oded Gabbay <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* doc: Set GL_OES_geometry_shader as startedMarta Lofstedt2015-11-301-1/+1
| | | | | Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* gles2: Update gl2ext.h to revision: 32120Marta Lofstedt2015-11-301-6/+934
| | | | | | | | | This is needed to be able to implement the accepted OES extensions. Cc: "11.0 11.1" <[email protected]> Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* vl/buffers: fixes vl_video_buffer_formats for RGBXJulien Isorce2015-11-301-1/+1
| | | | | | | Fixes: 42a5e143a8d "vl/buffers: add RGBX and BGRX to the supported formats" Cc: [email protected] Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965/fs: remove unused fs_reg offsetSamuel Iglesias Gonsálvez2015-11-301-1/+0
| | | | | Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Abdiel Janulgue <[email protected]>
* i965: Add src/dst interference for certain instructions with hazards.Kenneth Graunke2015-11-307-35/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When working on tessellation shaders, I created some vec4 virtual opcodes for creating message headers through a sequence like: mov(8) g7<1>UD 0x00000000UD { align1 WE_all 1Q compacted }; mov(1) g7.5<1>UD 0x00000100UD { align1 WE_all }; mov(1) g7<1>UD g0<0,1,0>UD { align1 WE_all compacted }; mov(1) g7.3<1>UD g8<0,1,0>UD { align1 WE_all }; This is done in the generator since the vec4 backend can't handle align1 regioning. From the visitor's point of view, this is a single opcode: hs_set_output_urb_offsets vgrf7.0:UD, 1U, vgrf8.xxxx:UD Normally, there's no hazard between sources and destinations - an instruction (naturally) reads its sources, then writes the result to the destination. However, when the virtual instruction generates multiple hardware instructions, we can get into trouble. In the above example, if the register allocator assigned vgrf7 and vgrf8 to the same hardware register, then we'd clobber the source with 0 in the first instruction, and read back the wrong value in the last one. It occured to me that this is exactly the same problem we have with SIMD16 instructions that use W/UW or B/UB types with 0 stride. The hardware implicitly decodes them as two SIMD8 instructions, and with the overlapping regions, the first would clobber the second. Previously, we handled that by incrementing the live range end IP by 1, which works, but is excessive: the next instruction doesn't actually care about that. It might also be the end of control flow. This might keep values alive too long. What we really want is to say "my source and destinations interfere". This patch creates new infrastructure for doing just that, and teaches the register allocator to add interference when there's a hazard. For my vec4 case, we can determine this by switching on opcodes. For the SIMD16 case, we just move the existing code there. I audited our existing virtual opcodes that generate multiple instructions; I believe FS_OPCODE_PACK_HALF_2x16_SPLIT needs this treatment as well, but no others. v2: Rebased by mattst88. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Fix JIP to properly skip over unrelated control flow.Kenneth Graunke2015-11-301-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've apparently always been botching JIP for sequences such as: do cmp.f0.0 ... (+f0.0) break ... if ... else ... endif ... while Normally, UIP is supposed to point to the final destination of the jump, while in nested control flow, JIP is supposed to point to the end of the current nesting level. It essentially bounces out of the current nested control flow, to an instruction that has a JIP which bounces out another level, and so on. In the above example, when setting JIP for the BREAK, we call brw_find_next_block_end(), which begins a search after the BREAK for the next ENDIF, ELSE, WHILE, or HALT. It ignores the IF and finds the ELSE, setting JIP there. This makes no sense at all. The break is supposed to skip over the whole if/else/endif block entirely. They have a sibling relationship, not a nesting relationship. This patch fixes brw_find_next_block_end() to track depth as it does its search, and ignore anything not at depth 0. So when it sees the IF, it ignores everything until after the ENDIF. That way, it finds the end of the right block. I noticed this while reading some assembly code. We believe jumping earlier is harmless, but makes the EU walk through a bunch of disabled instructions for no reason. I noticed that GLBenchmark Manhattan had a shader that contained a BREAK with a bogus JIP, but didn't measure any performance improvement (it's likely miniscule, if there is any). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* r600: move per-type settings into a switch statementDave Airlie2015-11-301-5/+13
| | | | | | | This will allow adding tess stuff much cleaner later. Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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