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* radeonsi: don't call force_dcc_off for buffersMarek Olšák2017-12-161-1/+1
* isl: Don't require VALIGN_2 for R32G32B32_FLOAT on Haswell.Kenneth Graunke2017-12-151-1/+3
* radeon/uvd: add and manage render picture listBoyuan Zhang2017-12-151-4/+25
* radeon/vcn: add and manage render picture listBoyuan Zhang2017-12-151-4/+24
* vl: remove is idr flagBoyuan Zhang2017-12-151-1/+0
* st/va: directly use idr pic flagBoyuan Zhang2017-12-151-5/+3
* radeon/vce: determine idr by pic typeBoyuan Zhang2017-12-151-1/+1
* radeon/vcn: determine idr by pic typeBoyuan Zhang2017-12-151-1/+1
* util: scons: wire up the sha1 testEmil Velikov2017-12-151-0/+7
* swr/rast: Move more RTAI handling out of binnerTim Rowley2017-12-152-12/+2
* swr/rast: EXTRACT2 changed from vextract/vinsert to vshuffleTim Rowley2017-12-153-61/+32
* swr/rast: Fix cache of API thread event managerTim Rowley2017-12-151-1/+1
* swr/rast: Replace VPSRL with LSHRTim Rowley2017-12-154-41/+4
* swr/rast: Rework thread binding parameters for machine partitioningTim Rowley2017-12-157-88/+322
* swr/rast: Pull of RTAI gather & offset out of clip/bin codeTim Rowley2017-12-157-146/+203
* swr/rast: Remove no-op VBROADCAST of vIDTim Rowley2017-12-151-2/+2
* swr/rast: SIMD16 Fetch - Fully widen 32-bit integer vertex componentsTim Rowley2017-12-154-17/+109
* swr/rast: Replace INSERT2 vextract/vinsert with JOIN2 vshuffleTim Rowley2017-12-153-105/+30
* swr/rast: SIMD16 Fetch - Fully widen 16-bit float vertex componentsTim Rowley2017-12-151-7/+48
* swr/rast: SIMD16 Fetch - Fully widen 32-bit float vertex componentsTim Rowley2017-12-154-32/+194
* swr/rast: Pass prim to ClipSimdTim Rowley2017-12-151-5/+5
* swr/rast: Pull most of the VPAI manipulation out of the binner/clipperTim Rowley2017-12-157-158/+177
* swr/rast: Move GatherScissors to headerTim Rowley2017-12-152-127/+127
* swr/rast: Rewrite Shuffle8bpcGatherd using shuffleTim Rowley2017-12-151-182/+62
* swr/rast: Convert gather masks to Nx1bitTim Rowley2017-12-152-40/+14
* swr/rast: WIP - Widen fetch shader to SIMD16Tim Rowley2017-12-151-27/+689
* swr/rast: Corrections to multi-scissor handlingTim Rowley2017-12-151-88/+88
* swr/rast: Binner fixes for viewport index offset handlingTim Rowley2017-12-152-2/+12
* swr/rast: Remove unneeded copy of gather maskTim Rowley2017-12-152-79/+23
* i965: Allow old begin/end queryobj for gen4/5 with HW contextsChris Wilson2017-12-151-6/+0
* freedreno: use u_transfer_helperRob Clark2017-12-152-229/+44
* gallium/util: add u_transfer_helperRob Clark2017-12-155-1/+649
* i965: enable EXT_disjoint_timer_query extensionTapani Pälli2017-12-151-0/+2
* mesa: GL_EXT_disjoint_timer_query extension API bitsTapani Pälli2017-12-156-1/+30
* glapi: add GL_EXT_disjoint_timer_queryTapani Pälli2017-12-153-2/+23
* mesa: add DisjointOperation to gl_shared_stateTapani Pälli2017-12-152-0/+9
* broadcom/vc5: Fix a typo in memcmp for sig unpack checking.Eric Anholt2017-12-141-1/+1
* broadcom/vc5: Enable NIR txd lowering on all txd instructions.Eric Anholt2017-12-141-0/+1
* nir: Add a new lowering option to lower all txd to txl.Eric Anholt2017-12-142-6/+14
* nir: Fix interaction of GL_CLAMP lowering with texture offsets.Eric Anholt2017-12-141-33/+42
* broadcom/vc5: Fix shader input/outputs for gallium's new NIR linking.Eric Anholt2017-12-141-4/+8
* gallivm: implement accurate corner behavior for textureGather with cube mapsRoland Scheidegger2017-12-141-103/+201
* gallivm: fix an issue with NaNs with seamless cube filteringRoland Scheidegger2017-12-141-0/+11
* intel/tools: Convert aubinator over to the common frameworkJason Ekstrand2017-12-143-690/+33
* intel/batch-decoder: Decode registersJason Ekstrand2017-12-141-0/+13
* intel/batch-decoder: Decode dynamic stateJason Ekstrand2017-12-141-0/+81
* intel/batch-decoder: Decode constants, binding tables, and samplersJason Ekstrand2017-12-141-0/+73
* intel/tools: Switch aubinator_error_decode over to the gen_print_batchJason Ekstrand2017-12-143-205/+37
* intel/batch-decoder: Decode graphics shadersJason Ekstrand2017-12-141-0/+95
* intel/batch-decoder: Decode vertex and index buffersJason Ekstrand2017-12-142-0/+161
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