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* vc4: Use the intrinsic's first_component for vattr VPM index.Eric Anholt2016-08-192-7/+3
| | | | Avoids another multiplication by 4 of the base in the NIR.
* vc4: Convert to using nir_lower_io_scalar for FS inputs.Eric Anholt2016-08-192-44/+62
| | | | | The scalarizing of FS inputs can be done in a non-driver-dependent manner, so extract it out of the driver.
* vc4: Switch to using the intrinsic accessors.Eric Anholt2016-08-193-23/+29
| | | | | The const_index[] values have always felt magic, and this documents them a bit better.
* nir: Add an IO scalarizing pass using the intrinsic's first_component.Eric Anholt2016-08-193-0/+131
| | | | | | | | | | vc4 wants to have per-scalar IO load/stores so that dead code elimination can happen on a more granular basis, which it has been doing in the backend using a multiplication by 4 of the intrinsic's driver_location. We can represent it properly in the NIR using the first_component field, though. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Add nir_builder support for individual system value loads.Eric Anholt2016-08-196-20/+34
| | | | | | | | | | The previous nir_load_system_value(b, nir_intrinsic_load_whatever), 0) was rather verbose, when system values should be easy to generate. The index is left out because only one system value had an index included in it. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Move the undef of nir_intrinsics.h macros to the .h.Eric Anholt2016-08-192-3/+3
| | | | | | | I wanted to include this from nir_builder as well, so it also needed the undefs. Reviewed-by: Kenneth Graunke <[email protected]>
* ttn: Use nir_load_front_face instead of the TGSI-style input.Eric Anholt2016-08-193-63/+28
| | | | | | | This reduces the diff between GLSL-to-NIR and TGSI-to-NIR, and gives NIR more optimization to work on. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Use the system-value front face for twoside lowering.Eric Anholt2016-08-191-16/+7
| | | | | | | | GLSL-to-NIR generates system value usage, and vc4/freedreno would both like the system value instead of the varying, so switch this pass over to it. Reviewed-by: Kenneth Graunke <[email protected]>
* ttn: Make FRAG_RESULT_DEPTH be a float variable to match gtn and ptn.Eric Anholt2016-08-194-11/+17
| | | | | | | This lets TTN-using drivers handle FRAG_RESULT_DEPTH the same between all their source paths. Reviewed-by: Rob Clark <[email protected]>
* vc4: Dump the TGSI before trying to convert it to NIR.Eric Anholt2016-08-191-4/+3
| | | | In the case of debugging a crash in TTN, this is nice to have.
* radeon/vce: set flag based on dual instance enablementBoyuan Zhang2016-08-191-2/+4
| | | | | | | Set the flag on when dual instance encoding is supported, otherwise set it to off. Signed-off-by: Boyuan Zhang <[email protected]>
* st/va: enable dual instances encode by sync surfaceBoyuan Zhang2016-08-193-3/+46
| | | | | | | | | | | This patch improves the performance of Vaapi Encode by enabling dual instances encoding. flush function is not called after each end_frame call. radeon/vce will do flush whenever 2 frames are submitted for encoding. Implement sync surface function to flush only if the frame hasn't been flushed yet. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* i965/blorp: Remove no longer used state setup helpersJason Ekstrand2016-08-193-657/+0
| | | | | | | | Now that we're using genxml for everything, we no longer need the hand-rolled state emit helpers. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use genxml for gen8-9 state setupJason Ekstrand2016-08-196-587/+172
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use genxml for gen7 state setupJason Ekstrand2016-08-196-565/+299
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add genxml-based vertex setup helpersJason Ekstrand2016-08-191-1/+212
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add a helper for emitting surface statesJason Ekstrand2016-08-191-24/+28
| | | | | | | | The new helper emits surface states and the binding table in one go. It's nice to have it pulled out of the main blorp_exec function. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add genxml-based sampler state emit functionJason Ekstrand2016-08-191-11/+38
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add genxml-based dynamic state emit functionsJason Ekstrand2016-08-191-9/+73
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Move gen6_blorp.c to a file that gets recompiled per-genJason Ekstrand2016-08-193-5/+18
| | | | | | | | | At the moment, it's only used for gen6 but that will change soon. We use the genX prefix for recompiled things in the Vulkan driver. It isn't great, but it seems to have worked ok. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp/gen6: Use genxml packing structs for state setupJason Ekstrand2016-08-192-420/+311
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Stop setting point and line rasterization rulesJason Ekstrand2016-08-193-7/+1
| | | | | | | | Blorp never uses points or lines and the default values of 0 are perfectly fine. Explicitly setting them is just noise. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp/gen8: Move viewport setup to after wm stateJason Ekstrand2016-08-191-1/+2
| | | | | | | This matches gen6 and gen7. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp/gen6-7: Move multisample setup to right after samplersJason Ekstrand2016-08-192-9/+10
| | | | | | | This mimics gen8 blorp Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp/gen6-7: Move surfaces and samplers closer togetherJason Ekstrand2016-08-192-11/+10
| | | | | | | This mimics what we do on gen8. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp/gen7-8: Emit depth stencil state with CC and BLENDJason Ekstrand2016-08-192-3/+4
| | | | | | | All three go together on SNB so let's keep them together for gen7+ as well. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp/gen6: Move constant disables higher upJason Ekstrand2016-08-191-22/+7
| | | | | | | This is what gen7-8 do and it's a bit cleaner. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Don't clear an empty regionJason Ekstrand2016-08-191-0/+4
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Move the non-static blorp state setup helpers to another fileJason Ekstrand2016-08-194-541/+578
| | | | | | | | We're about to start replacing blorp state setup code with packing structs and we want to feel free to delete files as we go. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Make gen6 VS and GS disable helpers staticJason Ekstrand2016-08-192-10/+2
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Roll intel_reg.h into brw_defines.hJason Ekstrand2016-08-1915-308/+277
| | | | | | | | More than half of the stuff in intel_reg.h had nothing whatsoever to do with registers and really belongs in brw_defines.h anyway. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Stop including brw_defines.h in brw_state.hJason Ekstrand2016-08-194-1/+3
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/state: Move is_drawing_lines/points to gen6_clip_state.cJason Ekstrand2016-08-194-56/+59
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml/gen9: Make 3DSTATE_SBE::AttributeActiveComponentFormat an arrayJason Ekstrand2016-08-192-67/+6
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Add a uint MOCS field to VERTEX_BUFFER_STATEJason Ekstrand2016-08-195-0/+5
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Make a couple of VERTEX_BUFFER_STATE fields booleanJason Ekstrand2016-08-195-7/+7
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Make VERTEX_ELEMENT_STATE::Valid a boolJason Ekstrand2016-08-195-5/+5
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml/gen6: Make SAMPLER_STATE look a bit more like gen7Jason Ekstrand2016-08-191-19/+26
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Add a uint MOCS field to DEPTH_BUFFER packetsJason Ekstrand2016-08-195-0/+10
| | | | | | | This is easier than dealing with structs all the time Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml/gen6: Make "Depth Clear Value" a uintJason Ekstrand2016-08-191-1/+1
| | | | | | | | The actual data storred is in float, UNORM24, or UNORM16 depending on the actual depth format. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml/gen6: Add the 3D_Prim_Topo_Type enumJason Ekstrand2016-08-191-0/+24
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml/gen6: Fix the length of 3DSTATE_WMJason Ekstrand2016-08-191-2/+2
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml/gen6: Add a Surface Base Address field to HIER_DEPTH_BUFFERJason Ekstrand2016-08-191-2/+3
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml/gen6: Add uint MOCS fields for most thingsJason Ekstrand2016-08-191-0/+6
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Rely on the fact that bcsel takes a well formed boolean.Kenneth Graunke2016-08-191-3/+3
| | | | | | | | | | | | | | | According to Connor, it's safe to assume that the first operand of bcsel, as well as the operand of b2f and b2i, must be well formed booleans. https://lists.freedesktop.org/archives/mesa-dev/2016-August/125658.html With the previous improvements to a@bool handling, this now has no change in shader-db instruction counts on Broadwell. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/sched: Change the scheduling heuristics to favor early program termination.Francisco Jerez2016-08-181-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This uses the unblocked time of the exit assigned to each available node to attempt to unblock exit nodes as early as possible, potentially reducing the runtime of the shader when an exit branch is taken. There is a natural trade-off between terminating the program as early as possible and reducing the worst-case latency of the program as a whole (since this will typically move exit-unblocking nodes closer to its dependencies potentially causing additional stalls of the execution pipeline), but in practice the bandwidth and ALU cycle savings from terminating the program earlier tend to outweigh the slight increase in worst-case program execution latency, so it makes sense to prefer nodes likely to unblock an earlier exit regardless of the latency benefits of other available nodes. I haven't observed any benchmark regressions from this change after testing on VLV, HSW, BDW, BSW and SKL. The FPS of the GfxBench Manhattan benchmark increases by 10%-20% and the FPS of Unigine Valley improves by roughly 5% depending on the platform and settings. The change to the register pressure-sensitive heuristic is rather conservative and gives precedence to the existing heuristic in order to avoid increasing register pressure and causing spill count and SIMD width regressions in shader-db. It may make sense to revisit this with additional performance data. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/sched: Assign a preferred exit node to each node of the dependency graph.Francisco Jerez2016-08-181-0/+59
| | | | | | | | | | | | | This adds a bit of metadata to schedule_node that will be used to compare available nodes in the scheduling heuristic code based on which of them unblocks the earliest successor exit node. Note that assigning exit nodes wouldn't be necessary in a bottom-up scheduler because we could achieve the same effect by scheduling the exit nodes themselves appropriately. No shader-db changes. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/sched: Calculate the critical path of scheduling nodes non-recursively.Francisco Jerez2016-08-181-13/+12
| | | | | | | | | | | | | | | | | | | The critical path of each node is calculated by induction based on the critical paths of its children, which can be done in a post-order depth-first traversal of the dependency graph. The current code implements graph traversal by iterating over all nodes of the graph and then recursing into its children -- But it turns out that recursion is unnecessary because the lexical order of instructions in the block is already a good enough reverse post-order of the dependency graph (if it weren't a reverse post-order some instruction would have been located before one of its dependencies in the original ordering of the basic block, which is impossible), so we just need to walk the instruction list in reverse to achieve the same result more efficiently. No shader-db changes. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Switch to per-subspan discard jumps.Francisco Jerez2016-08-181-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ANY4H is more efficient than ANY8H and ANY16H because it makes sure that whenever a whole subspan hits a discard statement it gets disabled by the EU until the end of the program, regardless of whether the discard condition is uniform across all channels of the SIMD8-16 thread. OTOH ANY8H/ANY16H would cause the rest of the program to be executed for *all* channels if only one of the channels hadn't taken the discard branch, potentially increasing the bandwidth and ALU usage of the program unnecessarily. This change increases the FPS by over 3x of a simple micro-benchmark that discards a bunch of fragments and then does a single costly texturing operation. I've just re-verified the FPS change on HSW and SKL, but I expect all platforms from Gen6 up to get a similar benefit. Note that we could potentially be more aggressive and use the NORMAL predicate to discard individual channels, but that would need to happen post-scheduling because the scheduler currently doesn't care to reorder HALT instructions with respect to other instructions, and the NORMAL predicate would cause the results of subsequent derivative computations to become undefined -- If the scheduler didn't reorder HALT instructions it would actually be safe to switch to NORMAL because the behavior of derivative computations after a non-uniform discard statement is undefined by the GLSL spec, but that would make the optimization implemented by one of the following commits somewhat more difficult. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Drop bogus writemasking disable bit from HALT instructions.Francisco Jerez2016-08-181-4/+0
| | | | | | | | | | This may have been the reason people ran into problems with non-uniform HALT instructions and ended up using the inefficient ANY16H/ANY8H predicates instead of ANY4H or NORMAL in order to prevent non-uniform discard. The HALT instruction is able to handle non-uniform execution masks just fine. Reviewed-by: Jason Ekstrand <[email protected]>
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