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* i965: Fix invalid memory accesses after resizing brw_codegen's store tableKristian Høgsberg2015-10-301-4/+13
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/sched: use liveness analysis for computing register pressureConnor Abbott2015-10-301-56/+229
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we were using some heuristics to try and detect when a write was about to begin a live range, or when a read was about to end a live range. We never used the liveness analysis information used by the register allocator, though, which meant that the scheduler's and the allocator's ideas of when a live range began and ended were different. Not only did this make our estimate of the register pressure benefit of scheduling an instruction wrong in some cases, but it was preventing us from knowing the actual register pressure when scheduling each instruction, which we want to have in order to switch to register pressure scheduling only when the register pressure is too high. This commit rewrites the register pressure tracking code to use the same model as our register allocator currently uses. We use the results of liveness analysis, as well as the compute_payload_ranges() function that we split out in the last commit. This means that we compute live ranges twice on each round through the register allocator, although we could speed it up by only recomputing the ranges and not the live in/live out sets after scheduling, since we only shuffle around instructions within a single basic block when we schedule. Shader-db results on bdw: total instructions in shared programs: 7130187 -> 7129880 (-0.00%) instructions in affected programs: 1744 -> 1437 (-17.60%) helped: 1 HURT: 1 total cycles in shared programs: 172535126 -> 172473226 (-0.04%) cycles in affected programs: 11338636 -> 11276736 (-0.55%) helped: 876 HURT: 873 LOST: 8 GAINED: 0 v2: use regs_read() in more places. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: split out calculation of payload live rangesConnor Abbott2015-10-302-22/+31
| | | | | | | | We'll need this for the scheduler too, since it wants to know when the live ranges of payload registers end in order to model them in our register pressure calculations. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: dump scheduling cycle estimatesConnor Abbott2015-10-304-10/+36
| | | | | | | | | | | | | The heuristic we're using is rather lame, since it assumes everything is non-uniform and loops execute 10 times, but it should be enough for measuring improvements in the scheduler that don't result in a change in the number of instructions. v2: - Switch loops and cycle counts to be compatible with older shader-db. - Make loop heuristic 10x to match with spilling code. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: always run the post-RA schedulerConnor Abbott2015-10-301-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Before, we would only do scheduling after register allocation if we spilled, despite the fact that the pre-RA scheduler was only supposed to be for register pressure and set the latencies of every instruction to 1. This meant that unless we spilled, which we rarely do, then we never considered instruction latencies at all, and we usually never bothered to try and hide texture fetch latency. Although a later commit removes the setting the latency to 1 part, we still want to always run the post-RA scheduler since it's able to take the false dependencies that the register allocator creates into account, and it can be more aggressive than the pre-RA scheduler since it doesn't have to worry about register pressure at all. Test master post-ra-sched diff %diff bench_OglPSBump2 396.730 402.386 5.656 +1.400% bench_OglPSBump8 244.370 247.591 3.221 +1.300% bench_OglPSPhong 241.117 242.002 0.885 +0.300% bench_OglPSPom 59.555 59.725 0.170 +0.200% bench_OglShMapPcf 86.149 102.346 16.197 +18.800% bench_OglVSTangent 388.849 395.489 6.640 +1.700% bench_trex 65.471 65.862 0.390 +0.500% bench_trexoff 69.562 70.150 0.588 +0.800% bench_heaven 25.179 25.254 0.074 +0.200% Reviewed-by: Jason Ekstrand <[email protected]>
* i965/sched: write-after-read dependencies are freeConnor Abbott2015-10-301-5/+5
| | | | | | | | | | | | Although write-after-write dependencies have the same latency as read-after-write dependencies due to how the register scoreboard works, write-after-read dependencies aren't checked by the EU at all, so they're purely a constraint on how the scheduler can order the instructions. v2: fix accumulator dependencies too. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: fix cycle estimates when there's a pipeline stallConnor Abbott2015-10-301-7/+8
| | | | | | | | | | | | The issue time for an instruction is how many cycles it takes to actually put it into the pipeline. If there's a pipeline stall that causes the instruction to be delayed, we should first take that into account to figure out when the instruction would start executing and *then* add the issue time. The old code had it backwards, and so we would underestimate the total time whenever we thought there would be a pipeline stall by up to the issue time of the instruction. Reviewed-by: Jason Ekstrand <[email protected]>
* vc4: Allow user index buffers, to avoid slow readback for shadow IBs.Eric Anholt2015-10-294-10/+25
| | | | | Improves low-settings openarena performance by 31.9975% +/- 0.659931% (n=7).
* nv50: mark contexts shareable, compile at creation timeIlia Mirkin2015-10-292-1/+4
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: allow per-sample interpolation to be forced via rastIlia Mirkin2015-10-298-9/+52
| | | | | | | | Uses the same technique as for nvc0 of fixups before upload, and evicting in case of state change. Removes one source of variants kept by st/mesa. Signed-off-by: Ilia Mirkin <[email protected]>
* i965: Add INTEL_DEBUG=nocompact to disable instruction compaction.Matt Turner2015-10-293-0/+5
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add INTEL_DEBUG=hex to print the hex with the disassembly.Matt Turner2015-10-293-1/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Print the type and writemask on null destinations.Matt Turner2015-10-291-1/+1
| | | | | | | | These are often useful in debugging, and the writemask (actually "Channel Enables") determines more than just what goes into the destination. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Test fixed_hw_reg.file against BRW_IMMEDIATE_VALUE, not IMM.Matt Turner2015-10-291-4/+4
| | | | | | | | No functional change, since they were both 3, but BRW_IMMEDIATE_VALUE is the hardware value and IMM was the IR value -- and you can see that BRW_IMMEDIATE_VALUE was correctly used in the context of this patch. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Test against BRW_IMMEDIATE_VALUE, not IMM.Matt Turner2015-10-291-1/+1
| | | | | | | | No functional change, since they were both 3, but BRW_IMMEDIATE_VALUE is the hardware value and IMM was the IR value -- and you can see that BRW_IMMEDIATE_VALUE was correctly used in the context of this patch. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Use group(4, 0) to emit an exec-size 4 MOV.Matt Turner2015-10-291-2/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cfg: Handle no-idom case in cfg_t::dump_domtree().Matt Turner2015-10-291-1/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Remove unused _addr_mode argument from src_ia1().Matt Turner2015-10-291-3/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Set correct field for indirect align16 addrimm.Matt Turner2015-10-291-1/+1
| | | | | | This has been wrong since the initial import of the i965 driver. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Drop brw_set_default_* before popping insn state.Matt Turner2015-10-291-3/+0
| | | | | Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Remove unnecessary #includes from the generator.Matt Turner2015-10-291-8/+0
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* r600: enable SB for geom shaders on pre-evergreenDave Airlie2015-10-301-4/+0
| | | | | | | | | | I've checked with piglit and one tests fails, but it fails on evergreen as well, so will get fixed later. Otherwise SB seems to be working fine for geom shaders on my rv635. Signed-off-by: Dave Airlie <[email protected]>
* i965/vec4: Eliminate the vec4_generator class altogether.Kenneth Graunke2015-10-291-284/+180
| | | | | | | | | | We really weren't taking advantage of vec4_generator being a class. By adding a "p" parameter to the helper methods, and "prog_data" to ones which need binding table information, we can convert everything to static functions. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Move vec4_generator class definition into the .cpp file.Kenneth Graunke2015-10-292-111/+110
| | | | | | | | | The public API for the generator is brw_vec4_generate_code(); nobody actually needs to use the class. This means we can extend it without triggering the recompiles associated with altering brw_vec4.h. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Wrap vec4_generator in a C function.Kenneth Graunke2015-10-294-9/+37
| | | | | | | | | vec4_generator is a class for convenience, but only exports a single method as its public API. It makes much more sense to just export a single function. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Convert src_reg/dst_reg to brw_reg at the end of the visitor.Kenneth Graunke2015-10-294-110/+92
| | | | | | | | | | | | | | | | | This patch makes the visitor convert registers to the HW_REG file at the very end, after register allocation, post-RA scheduling, and dependency control flagging. After that, everything is in fixed brw_regs. This simplifies the code generator, as it can just use the hardware registers rather than having to interpret our abstract files. In particular, interpreting the UNIFORM file meant reading prog_data to figure out where push constants are supposed to start. Having the part of the code that performs register allocation also translate everything to hardware registers seems sensible. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* r600g: Fix special negative immediate constants when using ABS modifier.Ivan Kalvachev2015-10-293-6/+6
| | | | | | | | | | | | | | | | | | | | | Some constants (like 1.0 and 0.5) could be inlined as immediate inputs without using their literal value. The r600_bytecode_special_constants() function emulates the negative of these constants by using NEG modifier. However some shaders define -1.0 constant and want to use it as 1.0. They do so by using ABS modifier. But r600_bytecode_special_constants() set NEG in addition to ABS. Since NEG modifier have priority over ABS one, we get -|1.0| as result, instead of |1.0|. The patch simply prevents the additional switching of NEG when ABS is set. [According to Ivan Kalvachev, this bug was fond via https://github.com/iXit/Mesa-3D/issues/126 and https://github.com/iXit/Mesa-3D/issues/127] Signed-off-by: Ivan Kalvachev <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> CC: <[email protected]>
* st/mesa: fix mipmap generation for immutable textures with incomplete pyramidsNicolai Hähnle2015-10-291-32/+36
| | | | | | | | | | | | | | | Without the clamping by NumLevels, the state tracker would reallocate the texture storage (incorrect) and even fail to copy the base level image after reallocation, leading to the graphical glitch of https://bugs.freedesktop.org/show_bug.cgi?id=91993 . A piglit test has been submitted for review as well (subtest of arb_texture_storage-texture-storage). v2: also bypass all calls to st_finalize_texture (suggested by Marek Olšák) Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* mesa: Enable ASTC in GLES' [NUM_]COMPRESSED_TEXTURE_FORMATS queriesNanley Chery2015-10-291-22/+63
| | | | | | | | | | | | | | | | In OpenGL ES, the COMPRESSED_TEXTURE_FORMATS query returns the set of supported specific compressed formats. Since ASTC formats fit within that category, include them in the set and update the NUM_COMPRESSED_TEXTURE_FORMATS query as well. This enables GLES2-based ASTC dEQP tests to run. See the Bugzilla for more info. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92193 Reported-by: Tapani Pälli <[email protected]> Suggested-by: Ian Romanick <[email protected]> Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa/texcompress: Restrict FXT1 format to desktop GL subsetNanley Chery2015-10-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In agreement with the extension spec and commit dd0eb004874645135b9aaac3ebbd0aaf274079ea, filter FXT1 formats to the desktop GL profiles. Now we no longer advertise such formats as supported in an ES context and then throw an INVALID_ENUM error when the client tries to use such formats with CompressedTexImage2D. Fixes the following 26 dEQP tests: * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_invalid_border * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_invalid_border_cube_neg_x * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_invalid_border_cube_neg_y * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_invalid_border_cube_neg_z * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_invalid_border_cube_pos_x * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_invalid_border_cube_pos_y * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_invalid_border_cube_pos_z * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_invalid_size * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_level_max_cube_pos * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_level_max_tex2d * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_level_cube * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_level_tex2d * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_width_height_cube_neg_x * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_width_height_cube_neg_y * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_width_height_cube_neg_z * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_width_height_cube_pos_x * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_width_height_cube_pos_y * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_width_height_cube_pos_z * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_width_height_tex2d * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_width_height_max_cube_neg_x * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_width_height_max_cube_neg_y * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_width_height_max_cube_neg_z * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_width_height_max_cube_pos_x * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_width_height_max_cube_pos_y * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_width_height_max_cube_pos_z * dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_width_height_max_tex2d v2. Use _mesa_is_desktop_gl() (Ilia, Ian) Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* nvc0: expose a group of performance metrics on FermiSamuel Pitoiset2015-10-293-3/+16
| | | | | | | This allows to monitor those performance metrics through GL_AMD_performance_monitor. Signed-off-by: Samuel Pitoiset <[email protected]>
* st/mesa: create temporary textures with the same nr_samples as sourceIlia Mirkin2015-10-291-2/+6
| | | | | | | | Not sure if this is actually reachable in practice (to have a complex copy with MS textures). Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* glsl: add fragdata arrays to program resource listTapani Pälli2015-10-291-0/+29
| | | | | | | | | | | | | | | This makes sure that user is still able to query properties about variables that have gotten removed by opt_dead_builtin_varyings pass. Fixes following OpenGL ES 3.1 test: ES31-CTS.program_interface_query.output-layout No Piglit regressions. v2: cleanup, drop extra parenthesis (Topi) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]>
* mesa: add fragdata_arrays list to gl_shaderTapani Pälli2015-10-292-16/+27
| | | | | | | | | | | | | This is required to store information about fragdata arrays, currently these variables get lost and cannot be retrieved later in sensible way for program interface queries. List will be utilized by next patch. Patch also modifies opt_dead_builtin_varyings pass to build list when lowering fragdata arrays. This is identical approach as taken with packed varyings pass. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]>
* glsl: fix GL_BUFFER_DATA_SIZE value for shader storage blocks with unsize arraysSamuel Iglesias Gonsalvez2015-10-291-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | From ARB_program_interface_query: "For the property of BUFFER_DATA_SIZE, then the implementation-dependent minimum total buffer object size, in basic machine units, required to hold all active variables associated with an active uniform block, shader storage block, or atomic counter buffer is written to <params>. If the final member of an active shader storage block is array with no declared size, the minimum buffer size is computed assuming the array was declared as an array with one element." Fixes the following dEQP-GLES31 tests: dEQP-GLES31.functional.program_interface_query.shader_storage_block.buffer_data_size.named_block dEQP-GLES31.functional.program_interface_query.shader_storage_block.buffer_data_size.unnamed_block dEQP-GLES31.functional.program_interface_query.shader_storage_block.buffer_data_size.block_array v2: - Fix comment's indentation and explain that the parser already checked that unsized array is in last element of a shader storage block (Iago). - Add assert (Iago). Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* docs: Mark GL_ARB_fragment_layer_viewport as done on i965.Kenneth Graunke2015-10-281-1/+1
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* i965: Implement ARB_fragment_layer_viewport.Kenneth Graunke2015-10-284-1/+46
| | | | | | | | | | | | | | Normally, we could read gl_Layer from bits 26:16 of R0.0. However, the specification requires that bogus out-of-range 32-bit values written by previous stages need to appear in the fragment shader as-written. Instead, we pass in the full 32-bit value from the VUE header as an extra flat-shaded varying. We have the SF override the value to 0 when the previous stage didn't actually write a value (it's actually defined to return 0). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Make calculate_attr_overrides return the URB read offset.Kenneth Graunke2015-10-284-10/+17
| | | | | | | | | | | | Traditionally, we've hardcoded "URB Entry Read Offset" to 1 (which represents 2 vec4 varying slots) to skip over the 8 DWord VUE header. In order to support ARB_fragment_layer_viewport, we'll need to read from that header. This patch adds the basic plumbing necessary to calculate a value dynamically and hook it up in the SBE packets. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* glsl: Mark gl_ViewportIndex and gl_Layer varyings as flat.Kenneth Graunke2015-10-281-12/+25
| | | | | | | | | Integer varyings need to be flat qualified - all others were already. I think we just missed this. Presumably some hardware passes this via sideband and ignores attribute interpolation, so no one has noticed. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Properly check for PAD in fragment shaders with > 16 varyings.Kenneth Graunke2015-10-281-4/+1
| | | | | | | | | | | | | | Commit 268008f98c3810b9f276df985dc93efc0c49f33e changed unused VUE map slots to be initialized with BRW_VARYING_SLOT_PAD, not COUNT. I missed updating this. It also means that commit message was wrong, as some code *did* rely slots being initialized to COUNT. This may fix a bug with SSO programs with > 16 FS input varyings. I think we probably just emitted extra pointless code, but probably didn't break anything. We might also just have no tests for that. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Update stale comment about unused VUE map slots.Kenneth Graunke2015-10-281-3/+1
| | | | | | | I changed this from COUNT to PAD in commit 268008f98c3810b9f276df985dc93ef. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* nv50/ir: adapt to new method for passing in cull/clip distance masksIlia Mirkin2015-10-294-14/+14
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: share shaders between contexts and build immediatelyIlia Mirkin2015-10-293-1/+7
| | | | | | | Avoid deferring building shaders until draw time, should hopefully reduce any stuttering, as well as enable shader-db style analysis. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: do upload-time fixups for interpolation parametersIlia Mirkin2015-10-2915-19/+239
| | | | | | | | | | | | | | | | | Unfortunately flatshading is an all-or-nothing proposition on nvc0, while GL 3.0 calls for the ability to selectively specify explicit interpolation parameters on gl_Color/gl_SecondaryColor which would override the flatshading setting. This allows us to fix up the interpolation settings after shader generation based on rasterizer settings. While we're at it, we can add support for dynamically forcing all (non-flat) shader inputs to be interpolated per-sample, which allows st/mesa to not generate variants for these. Fixes the remaining failing glsl-1.30/execution/interpolation piglits. Signed-off-by: Ilia Mirkin <[email protected]>
* nir: Copy "patch" flag from ir_variable to nir_variable.Kenneth Graunke2015-10-283-2/+5
| | | | | | | This was introduced in GLSL IR after NIR development had branched. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Add intrinsics for tessellation shader system values.Kenneth Graunke2015-10-282-7/+14
| | | | | | | | | | | | | | | | nir_intrinsic_load_patch_vertices_in corresponds to gl_PatchVerticesIn, a special input in both the TCS and TES stages. nir_intrinsic_load_tess_coord corresponds to gl_TessCoord, a special tessellation evaluation shader input. nir_intrinsic_load_tess_level_outer/inner correspond to the gl_TessLevelOuter[] and gl_TessLevelInner[] evaluation shader inputs, which we treat as system values because they're stored specially. (These intrinsics are only for the TES - the TCS uses output variables.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Fix missing BRW_NEW_*_PROG_DATA flagging caused by cache reuse.Kenneth Graunke2015-10-282-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consider the case of two nearly identical GLSL fragment shaders: out vec4 color; void main() { color = vec4(1); } and layout(early_fragment_tests) in; out vec4 color; void main() { color = vec4(1); } These shaders compile to the exact same assembly, but have distinct values for brw_wm_prog_data::early_fragment_tests. Since these are two independent GLSL shaders, they have different program keys - notably, brw_wm_prog_key::program_string_id differs. When uploading the second, brw_upload_cache will find an existing copy of the assembly in the cache BO, which means matching_data will be non-NULL. Although we create a second cache item (with the new key and prog_data), we set item->offset to the existing copy and avoid re-uploading duplicate assembly. However, brw_search_cache() would only flag BRW_NEW_*_PROG_DATA if item->offset differed from the supplied offset. With reuse, both programs have the same offset, but prog_data changed. We have to flag it, but failed to. To fix this, we simply need to check if the aux (prog_data) pointer changed. If either the assembly or the prog_data differs, flag it. This fixes a regression since 1bba29ed403e735ba0bf04ed8aa2e571884f, where Topi fixed brw_upload_cache() to actually reuse identical assembly. Prior to that, reuse basically never happened due to bugs. Unfortunately, this code apparently wasn't prepared to handle reuse! Fixes GPU hangs in Dolphin on Broadwell. Huge thanks to Pierre Bourdon and Ilia Mirkin for debugging this and helping track down the real issue. Cc: "11.0" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92623 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Tested-by: Pierre Bourdon <[email protected]>
* clover: fix building fix clang-3.8Laurent Carlier2015-10-291-1/+5
| | | | | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=92705 v2.1: use Linker::Flags::None instead of 0 and emplace_back() Signed-off-by: Laurent Carlier <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* nv50: add ARB_copy_image supportIlia Mirkin2015-10-283-8/+12
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add ARB_copy_image supportIlia Mirkin2015-10-283-8/+12
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
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