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* freedreno/a3xx: add support for dual-source blendingIlia Mirkin2015-09-168-6/+33
* vc4: convert from tgsi semantic/index to varying-slotEric Anholt2015-09-167-147/+106
* gallium/ttn: Convert to using VARYING_SLOT_* / FRAG_RESULT_*.Eric Anholt2015-09-166-47/+239
* nv50, nvc0: fix max texture buffer size to 128M elementsIlia Mirkin2015-09-162-2/+2
* st/mesa: avoid integer overflows with buffers >= 512MBIlia Mirkin2015-09-161-2/+2
* mesa: move GL_APPLE_object_purgeable functions to new fileBrian Paul2015-09-166-388/+461
* mesa: remove trailing whitespace in bufferobj.cBrian Paul2015-09-161-7/+7
* mesa: whitespace, line wrap fixes in varray.cBrian Paul2015-09-161-12/+20
* nir/print: print symbolic names from shader-enumRob Clark2015-09-161-3/+42
* nir/print: bit of state refactoringRob Clark2015-09-161-109/+152
* glsl: shader-enum to name debug fxnsRob Clark2015-09-164-1/+261
* freedreno: one screen to rule them allRob Clark2015-09-165-5/+126
* freedreno/ir3: use NIR to lower ffract instead of tgsi_loweringRob Clark2015-09-161-1/+1
* nir: add lowering for ffractRob Clark2015-09-162-0/+4
* i965/fs: The barrier send uses only 1 payload registerJordan Justen2015-09-152-2/+5
* nir/builder: Use a normal temporary array in nir_channelJason Ekstrand2015-09-151-1/+2
* freedreno/a4xx: more texture formatsRob Clark2015-09-151-7/+8
* freedreno/a4xx: border-color supportRob Clark2015-09-154-2/+31
* freedreno/a4xx: wire up texture clamp loweringRob Clark2015-09-152-20/+80
* freedreno: helper for a3xx/a4xx border-colorsRob Clark2015-09-154-67/+99
* freedreno: update generated headersRob Clark2015-09-155-17/+37
* nir/lower_vec_to_movs: Coalesce into destinations of fdot instructionsJason Ekstrand2015-09-151-13/+36
* i965/vec4: Use the replicated fdot instruction in NIRJason Ekstrand2015-09-152-3/+11
* nir: Add a fdot instruction that replicates the result to a vec4Jason Ekstrand2015-09-153-0/+12
* nir/lower_vec_to_movs: Coalesce movs on-the-fly when possibleJason Ekstrand2015-09-151-0/+85
* nir/lower_vec_to_movs: Get rid of start_idx and swizzle compactingJason Ekstrand2015-09-151-20/+13
* i965/vec4_nir: Use partial SSA form rather than full non-SSAJason Ekstrand2015-09-153-4/+20
* nir/lower_vec_to_movs: Handle partially SSA shadersJason Ekstrand2015-09-151-6/+15
* nir/lower_vec_to_movs: Pass the shader around directlyJason Ekstrand2015-09-151-6/+8
* i965/fs: Add a very basic validation passJason Ekstrand2015-09-154-0/+69
* i965/fs_surface_builder: Only apply predicate to components that existJason Ekstrand2015-09-151-1/+1
* i965/fs: Only read output_components many components when writing an outputJason Ekstrand2015-09-151-1/+3
* i965/fs: Set output_components for lowered clip distance outputsJason Ekstrand2015-09-151-0/+2
* mesa/teximage: restrict GL_ETC1_RGB8_OES support to GLESNanley Chery2015-09-151-1/+2
* mesa/extensions: restrict GL_OES_EGL_image to GLESNanley Chery2015-09-151-2/+1
* mesa/extensions: restrict luminance alpha formats to API_OPENGL_COMPATNanley Chery2015-09-152-4/+6
* gallium/svga: Enable PIPE_FORMAT_L8_UNORM for vgpu10Thomas Hellstrom2015-09-151-1/+1
* egl/dri2: don't leak the fd on dri2_terminateEmil Velikov2015-09-153-1/+3
* egl/dri2/drm: compact existing device mgmtEmil Velikov2015-09-151-6/+4
* egl/dri2: Close file descriptor on error.Matt Turner2015-09-151-13/+14
* gbm: convert gbm bo format to fourcc format on dma-buf importRay Strode2015-09-151-1/+17
* docs: document INTEL_DEBUG 'optimizer' envvarAlejandro Piñeiro2015-09-151-0/+1
* i965: Move perf_debug code to brw_codegen_*_prog()Kristian Høgsberg Kristensen2015-09-145-76/+75
* i965: Move brw_fs_precompile() to brw_wm.cKristian Høgsberg Kristensen2015-09-142-58/+59
* i965: Move compute shader code aroundKristian Høgsberg Kristensen2015-09-145-333/+362
* meta: Abort meta pbo path if TexSubImage need signed unsigned conversionAnuj Phogat2015-09-141-18/+25
* nvc0/ir: start offset at texBindBase for txq, like regular texturingIlia Mirkin2015-09-141-1/+4
* vc4: Fix build from recent NIR cleanups.Eric Anholt2015-09-141-2/+1
* i965/vec4_nir: Load constants as integersAntia Puentes2015-09-141-2/+2
* i965/vec4: Fix saturation errors when coalescing registersAntia Puentes2015-09-141-0/+21
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