Commit message (Collapse) | Author | Age | Files | Lines | |
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* | mesa: use _mesa_reference_buffer_object() in a few places | Brian Paul | 2009-06-12 | 3 | -4/+10 |
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* | tests: added persp_hint.c test | Brian Paul | 2009-06-12 | 3 | -0/+151 |
| | | | | Test the effect of GL_PERSPECTIVE_CORRECTION_HINT on color interpolation. | ||||
* | add some info to relnotes on radeon | Dave Airlie | 2009-06-13 | 1 | -0/+3 |
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* | r300: add support for EXT_texture_sRGB | Maciej Cencora | 2009-06-12 | 4 | -0/+27 |
| | | | | Tested with glean/texture_srgb and wine/d3d9 tests on RV535 | ||||
* | set/mesa: enable GL_NV_texture_env_combine4 | Brian Paul | 2009-06-12 | 1 | -0/+1 |
| | | | | | This is handled entirely in core Mesa where the combiner state is converted into a fragment program. | ||||
* | tests: added arbgpuprog, for compile-testing ARB vertex/fragment programs | Brian Paul | 2009-06-12 | 2 | -0/+231 |
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* | st/mesa: additional debug code (disabled) | Brian Paul | 2009-06-12 | 1 | -0/+20 |
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* | progs/rbug: Add binary to bmp converter program | Jakob Bornecrantz | 2009-06-12 | 3 | -0/+113 |
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* | Merge branch 'mesa_7_5_branch' | Jakob Bornecrantz | 2009-06-12 | 7 | -35/+125 |
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| * | mesa: Enable uploads of only depth to z24s8 textures | Jakob Bornecrantz | 2009-06-12 | 1 | -3/+36 |
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| * | mesa: rework vertex shader output / fragment shader input attribute matching | Brian Paul | 2009-06-11 | 1 | -20/+33 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before, if a vertex shader's outputs didn't exactly match a fragment shader's inputs we could wind up with invalid TGSI shader declarations. For example: Before patch: DCL OUT[0], POSITION DCL OUT[1], COLOR[1] DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[0] <- note duplicate [0] DCL OUT[4], GENERIC[2] After patch: DCL OUT[0], POSITION DCL OUT[1], COLOR[1] DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[1] DCL OUT[4], GENERIC[2] | ||||
| * | mesa: add default function for ctx->Driver.CheckQuery() hook | Brian Paul | 2009-06-11 | 3 | -1/+19 |
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| * | python/retrace: Show the contents of the depth/stencil and surfaces ↵ | José Fonseca | 2009-06-11 | 1 | -10/+28 |
| | | | | | | | | before/after transfers. | ||||
| * | python/retrace: Interpret is_texture_referenced/is_buffer_referenced. | José Fonseca | 2009-06-11 | 1 | -0/+8 |
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| * | wgl: Fix prototype. | José Fonseca | 2009-06-11 | 1 | -1/+1 |
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* | | Disable SGI_swap_control extension for DRI2 | Owen W. Taylor | 2009-06-12 | 1 | -1/+3 |
| | | | | | | | | | | | | | | | | | | We currently don't have support for SGI_swap_control for direct contexts with DRI2, so disable reporting the extension. Reporting the extension, and then having glXSwapIntervalSGI() "succeed" but do nothing can confuse applications. https://bugs.freedesktop.org/show_bug.cgi?id=22123 | ||||
* | | radeon: fix size of mipmap texture array | Dave Airlie | 2009-06-12 | 1 | -1/+3 |
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* | | radeon/r200/r300: fix max texture levels assert | Dave Airlie | 2009-06-12 | 2 | -6/+3 |
| | | | | | | | | use the actual value set in the context | ||||
* | | Merge remote branch 'main/radeon-rewrite' | Dave Airlie | 2009-06-12 | 120 | -18854/+16432 |
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| * | | r300: fix VAP setup | Maciej Cencora | 2009-06-11 | 1 | -5/+6 |
| | | | | | | | | | | | | If GL context had e.g. tex0, tex2 and fog the VAPOutputCntl1 returned 0x104 instead of 0x124 - that meaned we're sending only 8 texcoords (instead of 12) which ended up in GPU hang. | ||||
| * | | r300: fix for SW TCL path | Maciej Cencora | 2009-06-11 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | We shouldn't use i variable for SWTCL_OVM_TEX because textures doesn't have to be enabled in "packed" order. We could have tex1,tex3 and fog which would receive 7,9,8 OVM locations instead of 6,7,8. | ||||
| * | | r300: don't send unused attributes for SW TCL path | Maciej Cencora | 2009-06-11 | 1 | -14/+14 |
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| * | | r300: send only RS_IP_* regs that we are going to use | Maciej Cencora | 2009-06-11 | 2 | -10/+4 |
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| * | | r300: fix RS setup when no colors and textures are sent to FP | Maciej Cencora | 2009-06-11 | 1 | -4/+6 |
| | | | | | | | | | | | | RS_COL_FMT field is part of RS_IP_* reg not RS_INST_* | ||||
| * | | r300: r500 fragment program fixes | Maciej Cencora | 2009-06-11 | 1 | -12/+11 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - when rewriting per component negate swizzle, first instruction should get not negated source - KIL instruction ignores swizzles TODO: - tex instructions does not support saturation - tex instructions cannot read from consant memory | ||||
| * | | radeon: increase max bo count | Maciej Cencora | 2009-06-11 | 1 | -1/+1 |
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| * | | r300: fix a GPU lock up | Maciej Cencora | 2009-06-11 | 3 | -21/+24 |
| | | | | | | | | | | | | | | | | | | Sending from VAP more texture coordinates than RS expects results in GPU hang. Fixes BumpSelfShadow from DirectX8 SDK. | ||||
| * | | r300: fix vertex program bug | Maciej Cencora | 2009-06-11 | 1 | -6/+10 |
| | | | | | | | | | | | | | | | | | | If the vertex program didn't write position attribute, the position invariant function would add necessary instructions, but the vertex position would be overwritten by artificial outputs insts added to satisfy fragment program requirements. Fixes "whole screen is gray" problem for HW TCL path in sauerbraten when shaders are enabled, and whole slew of wine d3d9 tests. | ||||
| * | | r300: move some code for easier debugging | Maciej Cencora | 2009-06-11 | 1 | -17/+37 |
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| * | | r300: print vertex program when debugging is enabled | Maciej Cencora | 2009-06-11 | 1 | -3/+14 |
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| * | | r300: fix output register allocation for vertex shaders | Maciej Cencora | 2009-06-11 | 1 | -9/+19 |
| | | | | | | | | | | | | If the vertex program wrote secondary color without primary color, the secondary color output register index would be 0 which resulted in overwriting vertex position in some cases. | ||||
| * | | r300: hw doesn't support saturation for tex instructions | Maciej Cencora | 2009-06-11 | 1 | -0/+3 |
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| * | | r300: fix indexed primitive rendering when using memory manager | Jerome Glisse | 2009-06-11 | 1 | -2/+2 |
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| * | | r300: make sure indexed rendering doesn't try to use more than the num of ↵ | Jerome Glisse | 2009-06-10 | 1 | -0/+7 |
| | | | | | | | | | | | | | | | | | | | | | | | | vertices When with memory manager we need to make sure the GPU won't try to access beyond vertex buffer size, do so by enforcing that the maximun index is the last vertex of the buffer. | ||||
| * | | radeon: fix mipmap_limits crasher. | Dave Airlie | 2009-06-09 | 1 | -1/+1 |
| | | | | | | | | | | | | This gets the correct srclvl image map when uploading images to the new mipmap. | ||||
| * | | r300: fix regression caused by 056bc77547c304021a0faf204897ed238a5cf424 | Maciej Cencora | 2009-06-08 | 1 | -0/+1 |
| | | | | | | | | | | | | Fixes GPU hangs in software TCL path | ||||
| * | | Merge remote branch 'origin/master' into radeon-rewrite | Dave Airlie | 2009-06-07 | 291 | -8087/+16052 |
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| * | | | r300: Endianness fixes for recent vertex path changes. | Michel Dänzer | 2009-06-07 | 2 | -9/+37 |
| | | | | | | | | | | | | | | | | Signed-off-by: Maciej Cencora <[email protected]> | ||||
| * | | | r300: vertex array stride = 0 means that data are tightly packed in the array | Maciej Cencora | 2009-06-07 | 1 | -5/+8 |
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| * | | | r300: GL_(U)SHORT and GL_(U)BYTE with < 4 components can also be HW accelerated | Maciej Cencora | 2009-06-07 | 1 | -20/+29 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also when index format is GL_UBYTE, convert it to GL_USHORT not GL_UINT. Fix license header too. Reported by: Nicolai Hähnle <[email protected]> | ||||
| * | | | r300: remove unused code | Maciej Cencora | 2009-06-07 | 4 | -55/+1 |
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| * | | | r300: rewrite vertex setup for software T&L path using functions from ↵ | Maciej Cencora | 2009-06-07 | 4 | -209/+54 |
| | | | | | | | | | | | | | | | | software TCL path | ||||
| * | | | r300: prepare for some code duplication removal | Maciej Cencora | 2009-06-07 | 2 | -5/+15 |
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| * | | | r300: enable EXT_vertex_array_bgra extensions | Maciej Cencora | 2009-06-07 | 1 | -0/+1 |
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| * | | | r300: add hw accelerated support for different vertex data formats | Maciej Cencora | 2009-06-07 | 7 | -57/+485 |
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| * | | | r300: prepare for different vertex data type support | Maciej Cencora | 2009-06-07 | 6 | -120/+116 |
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| * | | | r300: fixup vertex attributes ordering | Maciej Cencora | 2009-06-07 | 1 | -17/+10 |
| | | | | | | | | | | | | | | | | Always allocate the vertex program input registers in the same order as the vertex attributes are passed in vertex arrays. | ||||
| * | | | r300: always pass 4 color components to RS unit | Maciej Cencora | 2009-06-07 | 1 | -42/+6 |
| | | | | | | | | | | | | | | | | Even if we don't pass all 4 color components to vertex shader unit, the vertex program can generate the missing components. | ||||
| * | | | radeon: Provide a more detailled GL_RENDERER string. | Nicolai Hähnle | 2009-06-01 | 3 | -5/+47 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Display the chip family and PCI ID. This can be parsed easily, and essentially all information that the driver has about the chip can be deduced from it. Signed-off-by: Nicolai Hähnle <[email protected]> | ||||
| * | | | r300: when using cs path emit scissor in the cmdbuffer | Jerome Glisse | 2009-05-28 | 4 | -0/+43 |
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