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* amdgpu/addrlib: Add a new tile mode ADDR_TM_UNKNOWNFrans Gu2017-03-308-14/+211
* amdgpu/addrlib: Stylish cleanup.Xavi Zhang2017-03-305-17/+16
* amdgpu/addrlib: Disable tcComaptible when depth surface is not macro tiledRoy Zhan2017-03-301-17/+20
* amdgpu/addrlib: fix pixel index calculation of thick micro tilingXavi Zhang2017-03-301-4/+4
* amdgpu/addrlib: Add a flag to skip calculate indicesXavi Zhang2017-03-303-14/+21
* amdgpu/addrlib: add equation generationNicolai Hähnle2017-03-3012-118/+1344
* amdgpu/addrlib: rename ComputeSurfaceThickness to ThicknessNicolai Hähnle2017-03-305-32/+32
* amdgpu/addrlib: add define HAVE_TSERVERXavi Zhang2017-03-302-6/+6
* amdgpu/addrlib: Add new interface to support macro mode index queryFrans Gu2017-03-304-0/+115
* amdgpu/addrlib: add explicit Log2NonPow2 functionRoy Zhan2017-03-301-8/+20
* amdgpu/addrlib: Fix invalid access to m_tileTableNicolai Hähnle2017-03-301-6/+17
* amdgpu/addrlib: add ADDR_ANALYSIS_ASSUMENicolai Hähnle2017-03-303-10/+20
* amdgpu/addrlib: add tcCompatible htile addr from coordinate support.XiaoYuan Zheng2017-03-305-13/+80
* amdgpu/addrlib: force all zero tile info for linear general.Carlos Xiong2017-03-301-1/+10
* amdgpu/addrlib: Add a member "bpp" for input of method AddrConvertTileIndex a...Nicolai Hähnle2017-03-307-32/+53
* amdgpu/addrlib: Refine the PRT tile mode selectionFrans Gu2017-03-302-51/+19
* amdgpu/addrlib: add dccRamSizeAligned output flagXavi Zhang2017-03-302-1/+7
* amdgpu/addrlib: Change comment alignmentNicolai Hähnle2017-03-301-12/+12
* amdgpu/addrlib: style changes and minor cleanupsNicolai Hähnle2017-03-3011-84/+82
* amdgpu/addrlib: AddrLib inheritance refactorNicolai Hähnle2017-03-309-560/+675
* amdgpu/addrlib: rearrange code in preparation of refactoringNicolai Hähnle2017-03-305-3528/+3595
* amdgpu/addrlib: add disableLinearOpt flagXavi Zhang2017-03-303-3/+8
* amdgpu/addrlib: Add GetMaxAlignmentsXavi Zhang2017-03-308-1/+184
* amdgpu/addrlib: Let Kaveri go general stereo right eye offset padding pathXavi Zhang2017-03-304-54/+41
* amdgpu/addrlib: Rewrite tile mode optmization codeXavi Zhang2017-03-307-34/+57
* amdgpu/addrlib: Add a flag "tcCompatible" to surface info output structure.Carlos Xiong2017-03-303-15/+50
* amdgpu/addrlib: Make comments shorterXavi Zhang2017-03-301-47/+29
* amdgpu/addrlib: add new flag nonSplitXiaoYuan Zheng2017-03-302-2/+3
* amdgpu/addrlib: allow tileSplitBytes greater than row sizeXiao-Tao Zai2017-03-301-1/+1
* amdgpu/addrlib: Change to compute TC compatible stencil infoCarlos Xiong2017-03-302-65/+59
* amdgpu/addrlib: rename SiAddrLib/CiAddrLib to match internal spellingNicolai Hähnle2017-03-304-149/+149
* configure.ac: require libdrm_amdgpu 2.4.76 for VegaMarek Olšák2017-03-301-1/+1
* st/glsl_to_tgsi: use glsl_type::sampler_index()Samuel Pitoiset2017-03-301-66/+2
* glsl: allow glsl_type::sampler_index() with imagesSamuel Pitoiset2017-03-301-1/+1
* st/mesa: improve error messages and fix security warningNicolai Hähnle2017-03-301-2/+2
* i965: Combine intel_batchbuffer_reloc and intel_batchbuffer_reloc64Kenneth Graunke2017-03-303-53/+19
* i965: Use WARN_ONCE instead of open coding it.Kenneth Graunke2017-03-301-9/+4
* android: pass sse4.1 flag as appropriateHarish Krupo2017-03-301-0/+3
* radv: fix mask attribs properly.Dave Airlie2017-03-301-2/+2
* radv: fix regression with mask attrib setting code.Dave Airlie2017-03-301-3/+3
* radv: move to using nir clip/cull merge pass.Dave Airlie2017-03-302-112/+40
* swr: [scons] Fix windows buildGeorge Kyriazis2017-03-291-7/+31
* anv/cmd_buffer: fix host memory leakCraig Stout2017-03-291-1/+9
* mesa/glthread: fallback to sync if count validation failsTimothy Arceri2017-03-301-8/+14
* mesa/glthread: add async support to glProgramUniform*() functionsTimothy Arceri2017-03-301-34/+34
* mesa/glthread: print out syncs when MARSHAL_MAX_CMD_SIZE is exceededTimothy Arceri2017-03-302-0/+14
* anv/batch_chain: Handle another OOM in cmd_buffer_execbufJason Ekstrand2017-03-291-2/+4
* st/mesa: EGLImageTarget* error handlingPhilipp Zabel2017-03-291-4/+19
* st/mesa: move st_manager_get_egl_image_surface into st_cb_eglimage.cPhilipp Zabel2017-03-293-37/+34
* i965: expose BRW_OPCODE_[F32TO16/F16TO32] name on gen8+Alejandro Piñeiro2017-03-291-0/+9
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