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* util/u_blitter: implement alpha blending for pipe->blitMarek Olšák2015-08-217-23/+49
* gallium: Add blending to pipe blitChristoph Bumiller2015-08-214-0/+5
* st/nine: Revert to sw cursor in case of failure to set hw cursorAxel Davy2015-08-211-2/+2
* st/nine: Do not call ID3DPresent_GetCursorPos for sw cursorAxel Davy2015-08-211-3/+4
* st/nine: Force hw cursor for Windowed modeAxel Davy2015-08-211-3/+9
* st/nine: Hide hardware cursor when we don't use itAxel Davy2015-08-211-6/+12
* st/nine: fix D3DRS_DITHERENABLE wrong state groupAxel Davy2015-08-211-1/+1
* st/nine: Account POINTSIZE_MIN and POINTSIZE_MAX for point sizePatrick Rudolph2015-08-213-14/+19
* st/nine: Align texture memoryPatrick Rudolph2015-08-214-6/+6
* st/nine: Always set point_quad_rasterization to 1Axel Davy2015-08-211-1/+1
* st/nine: Fix Swizzle for ATI2 formatAxel Davy2015-08-211-0/+5
* target/d3dadapter9: Return Windows like card namesPatrick Rudolph2015-08-213-42/+359
* st/nine: Require gcc >= 4.6David Heidelberg2015-08-211-0/+4
* glsl: fix error message when validating tcs output declsIlia Mirkin2015-08-211-1/+1
* relnote updatesRob Clark2015-08-211-1/+6
* st/mesa: pass through 4th opcode argument in bitmap/pixel visitorsIlia Mirkin2015-08-211-6/+6
* st/mesa: fix assignments with 4-operand arguments (i.e. BFI)Ilia Mirkin2015-08-211-1/+1
* i965: allow image_size on float imagesMartin Peres2015-08-211-1/+2
* clover: fix llvm 3.5 build errorZoltan Gilian2015-08-211-12/+21
* mesa: update fbo state in glTexStorageTapani Pälli2015-08-211-0/+15
* vc4: Add algebraic opt for rcp(1.0).Eric Anholt2015-08-201-0/+8
* vc4: Allow unpack_8[abcd]_f's src to stay in r4.Eric Anholt2015-08-201-1/+15
* vc4: Pack the unorm-packing bits into a src MUL instruction when possible.Eric Anholt2015-08-205-16/+104
* vc4: Add a QIR helper for whether the op is a MUL type.Eric Anholt2015-08-203-4/+16
* vc4: Drop an unused algebraic op.Eric Anholt2015-08-201-9/+0
* vc4: Switch QPU_PACK_SCALED to be two non-SSA instructions.Eric Anholt2015-08-205-21/+19
* vc4: Make the pack-to-unorm instructions be non-SSA.Eric Anholt2015-08-204-42/+36
* vc4: Allow QIR registers to be non-SSA.Eric Anholt2015-08-204-4/+10
* vc4: We can now move TEX_RESULT accesses across other r4 ops.Eric Anholt2015-08-201-16/+0
* glsl: fix binding validation for interface blocksTimothy Arceri2015-08-211-12/+18
* glsl: interleave constant propagation and foldingTimothy Arceri2015-08-211-2/+43
* nv50/ir: pre-compute BFE arg when both bits and offset are immIlia Mirkin2015-08-201-3/+9
* glsl: expose textureQueryLod in GLSL 4.00+ fragment shadersIlia Mirkin2015-08-201-37/+82
* Revert "mesa/formats: refactor by collapsing cases in switch statement by type"Nanley Chery2015-08-201-17/+135
* r600g: Fix handling of TGSI_OPCODE_ARR with SBGlenn Kennard2015-08-211-1/+1
* r600: Turn 'r600_shader_key' struct into unionEdward O'Callaghan2015-08-214-38/+42
* r600: Rewrite r600_shader_selector_key() to use a switch stmtEdward O'Callaghan2015-08-211-7/+17
* i965: Use NIR by default for vertex shadersJason Ekstrand2015-08-201-2/+2
* glsl: check if return_deref in lower_subroutine_visitor::visit_leave isn't NULLKai Wasserbäch2015-08-211-1/+1
* nv50/ir: Handle OP_CVT when folding constant expressionsTobias Klausmann2015-08-201-0/+78
* nvc0/ir: undo more shifts still by allowing a pre-SHL to occurIlia Mirkin2015-08-201-15/+33
* nvc0/ir: don't require AND when the high byte is being addressedIlia Mirkin2015-08-201-0/+12
* nvc0/ir: detect i2f/i2i which operate on specific bytes/wordsIlia Mirkin2015-08-204-4/+82
* nvc0/ir: detect AND/SHR pairs and convert into EXTBFIlia Mirkin2015-08-201-20/+46
* nv50/ir: support different unordered_set implementationsChih-Wei Huang2015-08-205-12/+57
* i965: Fix "handle nir_intrinsic_image_size"Martin Peres2015-08-201-4/+3
* i965: enable GL_ARB_shader_image_sizeMartin Peres2015-08-203-2/+4
* i965: handle nir_intrinsic_image_sizeMartin Peres2015-08-201-0/+46
* nir: convert the glsl intrinsic image_size to nir_intrinsic_image_sizeMartin Peres2015-08-202-6/+17
* glsl: add support for the imageSize builtinMartin Peres2015-08-201-16/+92
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