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* gallivm: Fix build against LLVM 3.7 SVN r235265Nick Sarnie2015-04-202-2/+2
| | | | | | | | | LLVM removed JITEmitDebugInfo from TargetOptions since they weren't used v2: Be consistent with the LLVM version check (Aaron Watry) Signed-off-by: Nick Sarnie <[email protected]> Reviewed-and-Tested-by: Michel Dänzer <[email protected]>
* doc: Add GL_ARB_shader_image_size dependency for OpenGL ES 3.1Ian Romanick2015-04-201-0/+1
| | | | | | imageSize() is in the GLSL ES 3.1 spec. Trivial. Signed-off-by: Ian Romanick <[email protected]>
* indices: fix provoking vertex for quads/quadstripsIlia Mirkin2015-04-181-3/+10
| | | | | | | | | | This allows drivers to provide consistent flat shading for quads. Otherwise a driver that only supported tris would have to force last provoking vertex when drawing quads (and would have to say that quads don't follow the provoking vertex convention). Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* primconvert: select pv convention only from flatshade_firstIlia Mirkin2015-04-181-2/+1
| | | | | | | | | This should match to how drivers program hardware. flatshade relates to whether color inputs are interpolated, not the provoking vertex convention. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: enable polymode setting with non-fill modesIlia Mirkin2015-04-181-0/+4
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: fix integer and 32-bit float border colorsIlia Mirkin2015-04-181-1/+30
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add support for float R/RG render targetsIlia Mirkin2015-04-181-4/+6
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* mesa: add .mesa-install-links files to gitignoreConnor Abbott2015-04-171-0/+1
| | | | | Signed-off-by: Connor Abbott <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa/main: add autogenerated format-info.c to gitignoreConnor Abbott2015-04-171-0/+1
| | | | | | | v2: move to right after format-info.h Signed-off-by: Connor Abbott <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* i965: Issue perf_debug messages for unsynchronized maps on !LLC systems.Kenneth Graunke2015-04-171-5/+11
| | | | | | | | | | | | | | | | | We haven't implemented proper unsynchronized map support on !LLC systems (pre-SNB, Atom). MapBufferRange with GL_MAP_UNSYNCHRONIZE_BIT will actually do a synchronized map, probably killing performance. Also warn on BufferSubData, when we should be doing an unsynchronized upload, but instead have to do a synchronous map. v2: Only complain if the buffer is actually busy - we use unsynchronized maps internally for vertex upload and such, but expect those to not be busy. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Tested-by: Ben Widawsky <[email protected]>
* i965: Make shader_time store names/ids instead of referencing shaders.Kenneth Graunke2015-04-172-37/+19
| | | | | | | | | | | | | | | | | | | | | Jason noticed that shader_time was bumping the reference count on the gl_shader_program and gl_program structures, in code called during compilation. Not only were these never unreferenced, but it meant fragment shaders might be referenced twice (SIMD8 and SIMD16)...or only once. We don't actually need the programs. We just need their numeric ID and their language (GLSL/ARB/FF) or KHR_debug label. If there's a label, we have to strdup it since the underlying program could be deleted. To be fair, we're not exactly cleaning that up either, but we at least ralloc it out of the shader_time arrays, so if we ever bother cleaning those up, they'll go away properly. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Delete some unnecessary code in brw_report_shader_time().Kenneth Graunke2015-04-171-6/+1
| | | | | | | | | | | | | It is true that a gl_shader_program with ID 0 will be a fixed-function fragment program; a gl_program with ID 0 but NULL gl_shader_program means that it's a fixed-function vertex shader. But that's not terribly interesting or relevant to what we're doing. We just need to know that ID 0 means "fixed function". Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Make shader_time use 0 instead of -1 for "no meaningful ID".Kenneth Graunke2015-04-171-8/+6
| | | | | | | | | | | | 0 is not a valid GLSL shader or ARB program ID. For some reason, shader_time used -1 instead...so we had code to detect 0, then override it to -1. We can just delete that. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* adjust a couple of ifdefs to handle NetBSD correctlyTobias Nygren2015-04-173-3/+3
| | | | | Acked-by: Matt Turner <[email protected]> Signed-off-by: Tobias Nygren <[email protected]>
* configure.ac: fix bashismTobias Nygren2015-04-171-1/+1
| | | | | Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Tobias Nygren <[email protected]>
* i965: Render R16G16B16X16 as R16G16B16A16Anuj Phogat2015-04-171-0/+6
| | | | | | | | | | This enables using _mesa_meta_pbo_TexSubImage() to upload data to R16G16B16X16 texture. Earlier it fell back to slower paths. Jenkins run shows no piglit regressions. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Update the comment about platforms supporting blorpAnuj Phogat2015-04-171-2/+2
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* nir: Allow abs/neg in select peephole pass.Matt Turner2015-04-171-1/+3
| | | | | | | | | | | total instructions in shared programs: 4314531 -> 4308949 (-0.13%) instructions in affected programs: 429085 -> 423503 (-1.30%) helped: 1680 HURT: 0 GAINED: 0 LOST: 111 Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Change SEL and MOV types as needed to propagate source modifiersJason Ekstrand2015-04-171-4/+30
| | | | | | | | | | | | | | | | | | | | SEL and MOV instructions, as long as they don't have source modifiers, are just copying bits around. This commit adds support to copy propagation to switch the type of a SEL or MOV instruction as needed so that it can propagate source modifiers. This is needed because NIR generates integer SEL and MOV instructions whenver it doesn't know what else to generate. shader-db results with NIR: total FS instructions in shared programs: 4360910 -> 4360186 (-0.02%) FS instructions in affected programs: 59094 -> 58370 (-1.23%) helped: 341 HURT: 0 GAINED: 2 LOST: 0 Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Use the source type when looking for UD negations in copy propJason Ekstrand2015-04-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There can be problems with floats and conditional modifiers when copy-propagating a negated UD source. The problem arises when a source modifier is applied to a UD value. In this case, a 33-bit representation is internally used. If you do the following: 1: mov foo:UD 7U 2: mov bar:UD -foo:UD 3: mov out:F bar:UD the out register will have the value (float)(unt32_t)-7 which is some very large floating-point number. However, if we allow copy-propagation of the second mov, we get 1: mov foo:UD 7U 3: mov out:f -bar:UD and, since the negation is computed in 33-bits, we get a value of -7.0f which is clearly not the same. This is a similar problem if the instruction has a conditional modifier where the 33-bit value is used in the comparison and not the 32-bit version. Previously, we checked the source to be copied for the negate and then checked the source being propagated to for the type. This isn't quite what we want because we are really just looking for negated UD sources. A check later in the file ensures that both ends of the propagate have the right type so it works. However, if we relax the restriction that both ends of the propagation have the same type, it ends up causing us to bail early in cases we don't want. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* freedreno/ir3/nir: few little fixesRob Clark2015-04-171-21/+28
| | | | | | | | | isaml needs to scale up coords based on LoD. Also fix bogus bary.f varying # when there are non-bary frag shader inputs. And use sub.s of a positive immediate rather than add.s of negative (since CP is better about figuring out that those can be collapsed into the cat2 instr). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: lower if/elseRob Clark2015-04-176-8/+381
| | | | | | | For now, completely flatten if/else blocks. That will almost certainly change once we have flow control. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: support for large shadersRob Clark2015-04-171-3/+26
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2015-04-178-42/+354
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: UBO supportRob Clark2015-04-172-0/+52
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move out helperRob Clark2015-04-172-24/+23
| | | | | | We'll also want it in NIR f/e for implementing UBO support. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: sysvals and UBOsRob Clark2015-04-173-24/+56
| | | | | | | | | | Basically just sync up the cmdstream emit parts to match the changes already done on a3xx. Also, fix scheduling for mem instructions. This is needed on a4xx, and I am a bit surprised it isn't needed for a3xx. Signed-off-by: Rob Clark <[email protected]>
* nir/builder: add nir_builder_insert_after_instr()Rob Clark2015-04-171-2/+18
| | | | | | | For lowering if/else, I need a way to insert at the end of the previous block. Signed-off-by: Rob Clark <[email protected]>
* gallium/ttn: fix TXFRob Clark2015-04-171-1/+7
| | | | | | | | There is a level param stashed away in the .w component of the first src. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium/ttn: add UBO supportRob Clark2015-04-171-9/+60
| | | | | | | | v2: move ishl into ttn (instead of driver backend) to keep the units consistent between immediate and indirect offsets Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium/ttn: minor cleanupRob Clark2015-04-171-23/+17
| | | | | | | | | | v2: also use ttn_src_for_indirect() everywhere for addr access, rather than open-coding it for INPUT/CONST srcs v3: move ralloc out of ttn_src_for_indirect() into the one call site that needs a ptr Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium/ttn: add support for TXL2Rob Clark2015-04-171-0/+11
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium/ttn: add support for texture offsetsRob Clark2015-04-171-1/+28
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa/st: Free st_translate with FREE macro.Brian Paul2015-04-171-1/+1
| | | | | | | | | To match CALLOC_STRUCT macro. Fixes memory corruption on Windows when u_memory's memory debugging is enabled. Reviewed-by: Jose Fonseca <[email protected]>
* libgl-gdi: Prevent "pure virtual method called" error when.Jose Fonseca2015-04-161-2/+20
| | | | | | | | | | When running piglit w/ llvmpipe on Windows several tests terminate abnormally just when the test exits. The problem was that LLVMContextDispose was being called after LLVM global destructors. Reviewed-by: Roland Scheidegger <[email protected]>
* i965: Add marketing names for CHVVille Syrjälä2015-04-161-4/+4
| | | | | | | All CHV devices will be branded as "Intel(r) HD Graphics". Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
* nir: Convert the if-test for num_inputs == 2 to an assertionIan Romanick2015-04-161-2/+2
| | | | | | | | | Suggested by Jason on a different patch after some comments / questions by Ilia. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* configure.ac: print LLVM_LDFLAGSMarek Olšák2015-04-161-0/+1
| | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* glsl_to_tgsi: only associate the uniform storage once at link timeMarek Olšák2015-04-161-24/+0
| | | | | | This hack is no longer needed. (see the previous commit) Reviewed-by: Brian Paul <[email protected]>
* glsl_to_tgsi: add STATE_FB_WPOS_Y_TRANSFORM at link timeMarek Olšák2015-04-161-20/+24
| | | | | | | This will allow removing the uniform storage re-association during TGSI generation at draw time. Reviewed-by: Brian Paul <[email protected]>
* glsl_to_tgsi: add assertions for detecting out-of-bounds immediates accessMarek Olšák2015-04-161-0/+6
| | | | Reviewed-by: Brian Paul <[email protected]>
* glsl_to_tgsi: don't use a potentially-undefined immediate for ir_query_levelsMarek Olšák2015-04-161-5/+3
| | | | | Cc: 10.4 10.5 <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* glsl_to_tgsi: fix out-of-bounds constant access and crash for uniformsMarek Olšák2015-04-161-4/+7
| | | | | | | | | This fixes piglit shaders@glsl-fs-uniform-array-loop-unroll with immediate shader compilation - it's a compiler test, so it has never been translated to TGSI before. Cc: 10.4 10.5 <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* glsl_to_tgsi: cleanup includesMarek Olšák2015-04-163-25/+10
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa/program: remove dead codeMarek Olšák2015-04-162-81/+0
| | | | Reviewed-by: Matt Turner <[email protected]>
* radeonsi: add a debug option to compile shaders when they're createdMarek Olšák2015-04-163-0/+6
| | | | Tested-by: Tom Stellard <[email protected]>
* st/mesa: add a debug option to compile shaders at link timeMarek Olšák2015-04-166-4/+55
| | | | | | | v2: fix crashes Tested-by: Tom Stellard <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* i965: Rewrite ir_tex to ir_txl with lod 0 for vertex shadersKristian Høgsberg2015-04-161-0/+9
| | | | | | | | | | | | | | | | The ir_tex opcode turns into a sample or sample_c message, which will try to compute derivatives to determine the lod. This produces garbage for non-fragment shaders where the sample coordinates don't correspond to subspans. We fix this by rewriting the opcode from ir_tex to ir_txl and setting the lod to 0. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89457 Cc: "10.5" <[email protected]> Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* radeonsi: remove bogus r600-- tripleEmil Velikov2015-04-161-2/+0
| | | | | | | | | | As mentioned by Michel Dänzer for LLVM >= 3.6 we create the LLVMTargetMachine (with triple amdgcn--), as we setup the radeonsi context. For older LLVM or hardware (r600) the triple is always r600-- and is created at a later stage - radeon_llvm_compile() Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* i965/skl: Add the header for constant loads outside of the generatorNeil Roberts2015-04-166-35/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 5a06ee738 added a step to the generator to set up the message header when generating the VS_OPCODE_PULL_CONSTANT_LOAD_GEN7 instruction. That pseudo opcode is implemented in terms of multiple actual opcodes, one of which writes to one of the source registers in order to set up the message header. This causes problems because the scheduler isn't aware that the source register is written to and it can end up reorganising the instructions incorrectly such that the write to the source register overwrites a needed value from a previous instruction. This problem was presenting itself as a rendering error in the weapon in Enemy Territory: Quake Wars. Since commit 588859e1 there is an additional problem that the double register allocated to include the message header would end up being split into two. This wasn't happening previously because the code to split registers was explicitly avoided for instructions that are sending from the GRF. This patch fixes both problems by splitting the code to set up the message header into a new pseudo opcode so that it will be done outside of the generator. This new opcode has the header register as a destination so the scheduler can recognise that the register is written to. This has the additional benefit that the scheduler can optimise the message header slightly better by moving the mov instructions further away from the send instructions. On Skylake it appears to fix the following three Piglit tests without causing any regressions: gs-float-array-variable-index gs-mat3x4-row-major gs-mat4x3-row-major I think we actually may need to do something similar for the fs backend and possibly for message headers from regular texture sampling but I'm not entirely sure. v2: Make sure the exec-size is retained as 8 for the mov instruction to initialise the header from g0. This was accidentally lost during a rebase on top of 07c571a39fa1. Split the patch into two so that the helper function is a separate change. Fix emitting the MOV instruction on Gen7. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89058 Reviewed-by: Ben Widawsky <[email protected]>
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