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* i965/nir/vec4: Implement load_uniform intrinsicIago Toral Quiroga2015-08-031-2/+24
| | | | | | | | | For the indirect case we need to take the index delivered by NIR and compute the parent uniform that we are accessing (the one that we uploaded to a surface) and the constant offset into that surface. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement intrinsics that load system valuesAlejandro Piñeiro2015-08-031-6/+21
| | | | | | | | | | | | | These include: nir_intrinsic_load_vertex_id_zero_base nir_intrinsic_load_base_vertex nir_intrinsic_load_instance_id The source register is fetched from the nir_system_values map initialized during nir_setup_system_values stage. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement store_output intrinsicEduardo Lima Mitev2015-08-032-3/+19
| | | | | | | | | | | | | | This implementation is based on the current URB setup in vec4_visitor, which requires the output register to be stored in the output_reg array at variable's original shader location index. But since nir_lower_io() pass uses the value in var->data.driver_location, we need to put there var->data.location instead, prior to calling nir_lower_io(), so that we end up with the correct index in const_index[0]. The driver_location is not used at all, so this patch also disables the nir_assign_var_locations pass on non-scalar shaders. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Make sure that register types always match during emit_urb_slot()Eduardo Lima Mitev2015-08-031-5/+10
| | | | | | | | | | | | Instead of relying on backends (currently vec4_visitor and soon NIR-vec4) to store registers in output_reg with the correct type, this patch makes sure that the common code in emit_urb_slot() always emit MOVs from output registers using the same type on source and destination. Since the actual type is not important, only that they match, we default to float. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement load_input intrinsicEduardo Lima Mitev2015-08-031-2/+20
| | | | | | | The source register is fetched from the nir_inputs map built during nir_setup_inputs stage. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement loop statements (nir_cf_node_loop)Eduardo Lima Mitev2015-08-031-1/+5
| | | | | | This is taken as-is from fs_nir. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement conditional statements (nir_cf_node_if)Iago Toral Quiroga2015-08-031-1/+15
| | | | | | | | The same we do in the FS NIR backend, only that here we need to consider the number of components in the condition and adjust the swizzle accordingly. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Add get_nir_dst() and get_nir_src() methodsEduardo Lima Mitev2015-08-032-0/+83
| | | | | | | | | | | | | These methods are essential for the implementation of the NIR->vec4 pass. They work similar to their fs_nir counter-parts. When processing instructions, these methods are invoked to resolve the brw registers (source or destination) corresponding to the NIR sources or destination. It uses the map of NIR register index to brw register for all registers locally allocated in a block. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir: Move brw_type_for_nir_type() to brw_nir to allow reuseEduardo Lima Mitev2015-08-033-18/+21
| | | | | | Upcoming NIR->vec4 pass can benefit from this method, so lets move it up. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement load_const intrinsicEduardo Lima Mitev2015-08-033-2/+20
| | | | | | | | | Similar to fs_nir backend, a nir_local_values map will be filled with newly allocated registers as the load_const instrinsic instructions are processed. Later, get_nir_src() will fetch the registers from this map for sources that are ssa. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Add auxiliary func to build a writemask from a component sizeEduardo Lima Mitev2015-08-031-0/+6
| | | | | | | New method brw_writemask_for_size() will return a writemask with the first 'size' components activated. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir: Dot not assign direct uniform locations first for vec4-based shadersIago Toral Quiroga2015-08-031-4/+10
| | | | | | | | | | In the vec4 backend we want uniform locations to be assigned consecutively since that way the offsets produced by nir_lower_io are exactly what we need to implement nir_intrinsic_load_uniform. Otherwise we would need a mapping to match the output of nir_lower_io to the actual uniform registers we need to use. Reviewed-by: Jason Ekstrand <[email protected]>
* nir/nir_lower_io: Add vec4 supportIago Toral Quiroga2015-08-033-33/+86
| | | | | | | | | | The current implementation operates in scalar mode only, so add a vec4 mode where types are padded to vec4 sizes. This will be useful in the i965 driver for its vec4 nir backend (and possbly other drivers that have vec4-based shaders). Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir: Pass a is_scalar boolean to brw_create_nir()Eduardo Lima Mitev2015-08-035-7/+12
| | | | | | | | | | | | The upcoming introduction of NIR->vec4 pass will require that some NIR lowering passes are enabled/disabled depending on the type of shader (scalar vs. vector). With this patch we pass a 'is_scalar' variable to the process of constructing the NIR, to let an external context decide how the shader should be handled. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Add shader function implementationEduardo Lima Mitev2015-08-032-1/+11
| | | | | | | It basically allocates registers local to a function in a nir_locals map, then emits all its control-flow blocks. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Add setup for system valuesAlejandro Piñeiro2015-08-032-1/+50
| | | | | | | | | Similar to other variable setups, system values will initialize the corresponding register inside a 'nir_system_values' map, which will then be queried later when processing the different system value intrinsics for the appropriate register. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Redefine make_reg_for_system_value() to allow reuse in NIR->vec4 passAlejandro Piñeiro2015-08-038-11/+19
| | | | | | | | | | | The new virtual method is more flexible, it has a signature: dst_reg *make_reg_for_system_value(int location, const glsl_type *type); v2 (Jason Ekstrand): Use the new version in unit tests so make check passes again Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Add setup of uniform variablesIago Toral Quiroga2015-08-032-3/+97
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Add setup of input variables in NIR->vec4 passEduardo Lima Mitev2015-08-032-1/+12
| | | | | | | | | | This implementation sets up a map of input variable offsets to source registers that are already initialized with the corresponding register offset. This map will then be queried when processing load_input intrinsic operations, to obtain the correct register source from which the input data will be loaded. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Move type_size() method to brw_vec4_visitor classEduardo Lima Mitev2015-08-032-6/+17
| | | | | | | | The type_size() method is currently accessible only in the implementation of vec4_visitor. Since we need to reuse it in the upcoming NIR->vec4 pass, lets make it a method of the class instead. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Select between new nir_vec4 or current vec4_visitor code-pathsEduardo Lima Mitev2015-08-032-10/+22
| | | | | | | | | | The NIR->vec4 pass will be activated if both the following conditions are met: * INTEL_USE_NIR environment variable is defined and is positive (1 or true) * The stage is vertex shader (support for geometry shaders and ARB_vertex_program will be added later). Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Add implementation placeholders for a new NIR->vec4 passEduardo Lima Mitev2015-08-033-0/+273
| | | | | | | | | | This patch will add a brw_vec4_nir.cpp file filled with entry point methods to the main functionality, following a structure similar to brw_fs_nir.cpp. Subsequent patches in this series will be adding the implementations for these methods, incrementally. Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: Replace F_TO_I() with _mesa_lroundevenf().Matt Turner2015-08-036-42/+42
| | | | | | | | | | | I'm not sure what the true meaning of "The rounding mode may vary." is, but it is the case that the IROUND() path rounds differently than the other paths (and does it wrong, at that). Like _mesa_roundeven{f,}(), just add an use _mesa_lroundeven{f,}() that has known semantics. Reviewed-by: Roland Scheidegger <[email protected]>
* mesa: Add -fno-trapping-math to CFLAGS.Matt Turner2015-08-031-2/+2
| | | | | | | | | | Cuts about 1k of .text size. text data bss dec hex filename 4983676 197808 26328 5207812 4f7704 i965_dri.so before 4982522 197800 26328 5206650 4f727a i965_dri.so after Reviewed-by: Roland Scheidegger <[email protected]>
* mesa: Add -fno-math-errno to CFLAGS.Matt Turner2015-08-031-0/+3
| | | | | | | | | | | | | Cuts about 9k of .text size. text data bss dec hex filename 4992804 197808 26328 5216940 4f9aac i965_dri.so before 4983676 197808 26328 5207812 4f7704 i965_dri.so after Also, Darwin's libm does not ever set errno, so if we care about those systems we shouldn't rely on errno anyway. Reviewed-by: Roland Scheidegger <[email protected]>
* r600,compute: force tiling on 2D and 3D texture compute resourcesZoltan Gilian2015-08-031-2/+9
| | | | | | | To circumvent a problem occuring when LINEAR_ALIGNED array mode is selected on a TEXTURE_2D RAT. This configuration causes MEM_RAT STORE_TYPED to write to incorrect locations.
* clover: handle setKernelArg errorsZoltan Gilian2015-08-031-0/+15
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* clover: fix image resource depth and array_sizeZoltan Gilian2015-08-032-1/+2
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* nir: Use a single bit for the dual-source blend indexTimothy Arceri2015-08-031-2/+6
| | | | | | | | | | The only values allowed are 0 and 1, and the value is checked before assigning. This is a copy of 8eeca7a56c that seems to have been made to the glsl ir type after it was copied for use in nir but before nir landed. Reviewed-by: Tapani Pälli <[email protected]>
* clover: pass image attributes to the kernelZoltan Gilian2015-08-034-11/+171
| | | | | | | Read-only and write-only image arguments are recognized and distinguished. Attributes of the image arguments are passed to the kernel as implicit arguments.
* clover: move find_kernels to functionsZoltan Gilian2015-08-031-13/+15
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* mesa: fix type for array indexing validationTimothy Arceri2015-08-031-1/+1
| | | | | | | | | | | | | parse_program_resource_name returns -1 when the index is invalid this needs to be tested before assigning the value to the unsigned array_index. In link_varyings.cpp (the other place parse_program_resource_name is used) after the -1 check is done the value is just assigned to an unsigned variable so it seems long is just used so we can return the -1 rather than actually expecting index values to be ridiculously large. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa/es3.1: Allow multisampled textures for GLES 3.1Marta Lofstedt2015-08-031-2/+2
| | | | | | | GLES 3.1 must be allowed to create multisampled textures. Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa/es3.1: Allow query of GL_TEXTURE_MULTISAMPLEMarta Lofstedt2015-08-031-1/+3
| | | | | | | GLES 3.1 must allow a query for GL_TEXTURE_MULTISAMPLE. Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa/es3.1: Allow enable of GL_SAMPLE_MASKMarta Lofstedt2015-08-031-1/+1
| | | | | | | GLES 3.1 must be able to enable GL_SAMPLE_MASK. Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa/es3.1: Allow textures with target GL_TEXTURE_2D_MULTISAMPLEMarta Lofstedt2015-08-032-3/+3
| | | | | | | | GLES 3.1 should be able to bind a texture with the target GL_TEXTURE_2D_MULTISAMPLE. Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa/es3.1: Allow GL_DEPTH_STENCIL_TEXTURE_MODEMarta Lofstedt2015-08-031-1/+3
| | | | | | | GLES 3.1 must support the parameter GL_DEPTH_STENCIL_TEXTURE_MODE. Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa/es3.1: Allow GL_SAMPLE_MASKMarta Lofstedt2015-08-031-1/+1
| | | | | | | GLES 3.1 should be allowed to enable GL_SAMPLE_MASK. Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa/es3.1: Allow binding GL_DRAW_INDIRECT_BUFFER with gles 3.1Marta Lofstedt2015-08-031-2/+3
| | | | | Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* r600g: re-enable single-sample fast clearMarek Olšák2015-08-031-6/+1
| | | | | | | Fixed by the CB_SHADER_MASK fix. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* r600g: fix the CB_SHADER_MASK setupMarek Olšák2015-08-032-4/+5
| | | | | | | | This fixes the single-sample fast clear hang. Cc: 10.6 <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* r600g: fix the single-sample fast clear setupMarek Olšák2015-08-031-2/+6
| | | | | | | No effect, but this is what we should be doing. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: flush if the memory usage for an IB is too highMarek Olšák2015-08-022-0/+17
| | | | | | | Picked from the amdgpu branch. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* opencl: use versioned .so in mesa.icdIgor Gnatenko2015-08-014-2/+5
| | | | | | | | | | | | We must have versioned library in mesa.icd, because ICD loader would fail if the mesa-devel package wasn't installed. Cc: "10.6" <[email protected]> Reported-by: Fabian Deutsch <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73512 Signed-off-by: Igor Gnatenko <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* includes/GL: remove duplicated extension declarations from glx.hEmil Velikov2015-08-011-92/+0
| | | | | | | | | | | | All three of GLX_NV_float_buffer, GLX_EXT_texture_from_pixmap and GLX_MESA_query_renderer have been in glxext.h for a while now. As such we can drop this workaround/hack from the header. v2: Remove the comment about GLX_NV_float_buffer. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Brian Paul <[email protected]> (v1)
* docs: rename/bump 10.7.0 release notes to 11.0.0Emil Velikov2015-08-012-7/+7
| | | | | | | | | | Recently a few drivers have grown OpenGL 4+ support so we might as well go all the way to... 11 ;-) v2: Don't forget to update the version file (Ilia) Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* winsys/radeon: don't leak the fd when it is 0Emil Velikov2015-08-011-2/+2
| | | | | | | | | | | | | | Earlier commit added an extra dup(fd) to fix a ZaphodHeads issue. Although it did not consider the (very unlikely) case where we might end up with the valid fd == 0. Fixes: 28dda47ae4d(winsys/radeon: Use dup fd as key in drm-winsys hash table to fix ZaphodHeads.) Cc: 10.6 <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Mario Kleiner <[email protected]>
* configure.ac: check for mkostemp()Emil Velikov2015-08-011-0/+1
| | | | | | | | We can make use of it over mkstemp + fcntl in the egl/wayland code. Cc: Axel Davy <[email protected]> Suggested-by: Matt Turner <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* egl/wayland: use drmGetNodeTypeFromFd helper instead of opencoding itEmil Velikov2015-08-012-19/+3
| | | | | | Cc: Axel Davy <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Acked-by: Boyan Ding <[email protected]>
* egl/wayland: use designated initializersEmil Velikov2015-08-011-13/+13
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Thomas Helland <[email protected]>
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