summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* amd/common: add ac_vgt_gs_mode() helperSamuel Pitoiset2017-12-184-55/+42
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: add ac_get_cb_shader_mask() helperSamuel Pitoiset2017-12-184-66/+40
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* Revert "radv: do not load unused gl_LocalInvocationID/gl_WorkGroupID components"Samuel Pitoiset2017-12-181-5/+2
| | | | | | | | | | | | | This reverts commit 2294d35b243dee15af15895e876a63b7d22e48cc. We can't do this without adjusting the input SGPRs/VGPRs logic. For now, just revert it. I will send a proper solution later. It fixes a rendering issue in F1 2017 that CTS didn't catch up. Signed-off-by: Samuel Pitoiset <[email protected]> Tested-by: Alex Smith <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: port merge tess info from anvDave Airlie2017-12-181-0/+40
| | | | | | | | | | | anv merges the tess info correctly, but radv wasn't doing this. This fixes hangs in dEQP-VK.tessellation.winding.default_domain.hlsl_triangles_ccw Fixes: 60fc0544e0 (radv/pipeline: handle tessellation shader compilation) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Add external fence support.Bas Nieuwenhuizen2017-12-182-0/+22
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement VK_KHR_external_fence_fd.Bas Nieuwenhuizen2017-12-182-0/+48
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement fences based on syncobjs.Bas Nieuwenhuizen2017-12-183-15/+109
| | | | Reviewed-by: Dave Airlie <[email protected]>
* amd/common: Add detection of the syncobj wait/signal/reset ioctls.Bas Nieuwenhuizen2017-12-182-0/+2
| | | | | | First amdgpu bump after inclusion was 20 (which was done for local BOs). Reviewed-by: Dave Airlie <[email protected]>
* radv: Add syncobj signal/reset/wait to winsys.Bas Nieuwenhuizen2017-12-182-0/+44
| | | | Reviewed-by: Dave Airlie <[email protected]>
* configure/meson: Bump libdrm_amdgpu version requirement.Bas Nieuwenhuizen2017-12-182-2/+2
| | | | | | For the radv dependencies on syncobj signal/reset. Reviewed-by: Dave Airlie <[email protected]>
* android: fix vulkan driver buildTapani Pälli2017-12-181-2/+3
| | | | | | | fixes undefined references by adding missing wsi common API Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* android: fix undefined references to futex APITapani Pälli2017-12-181-0/+1
| | | | | | Fixes: f98a2768ca "mesa: Add new fast mtx_t mutex type for basic use cases" Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* docs: mark GL4.3 as finished for r600Dave Airlie2017-12-182-23/+24
| | | | Still only on fp64 supported hw.
* r600: export robust buffer accessDave Airlie2017-12-182-2/+2
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600: export GLSL 430Dave Airlie2017-12-181-1/+1
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600/cs: add compute support to capsDave Airlie2017-12-181-2/+2
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600: always flush between gfx and computeDave Airlie2017-12-185-0/+21
| | | | | | | | This is in no way optimal, but there seems to be some problems mixing at the moment, lots of hangs, it is possible, just need to figure out more magic. Signed-off-by: Dave Airlie <[email protected]>
* r600: fix unused variable warningDave Airlie2017-12-181-1/+0
| | | | Signed-off-by: Dave Airlie <[email protected]>
* radv: Fix multi-layer blits.Bas Nieuwenhuizen2017-12-181-25/+24
| | | | | | | | | We did not set the layer correctly for the dst, as we would keep using the base layer. Same for the source image. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102710 CC: <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* freedreno/a5xx: add a5xx blitterRob Clark2017-12-178-1/+498
| | | | | | FD_MESA_DEBUG=noblit to disable Signed-off-by: Rob Clark <[email protected]>
* freedreno: add generic blitterRob Clark2017-12-177-2/+161
| | | | | | | Basically a clone of util_blitter_blit() but with special handling to blit PIPE_BUFFER as a PIPE_TEXTURE_1D. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add non-draw batches for compute/blitRob Clark2017-12-1712-32/+82
| | | | | | | | | Get rid of "gmem" (ie. tiling) ringbuffer, and just emit setup commands directly to "draw" ringbuffer for compute (and in future for blits not using the 3d pipe). This way we can have a simple flat cmdstream buffer and bypass setup related to 3d pipe. Signed-off-by: Rob Clark <[email protected]>
* freedreno: track staging and shadow perf ctrs for the HUDRob Clark2017-12-175-0/+16
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: staging upload transfersRob Clark2017-12-173-43/+135
| | | | | | | | | | In the busy && !needs_flush case, we can support a DISCARD_RANGE upload using a staging buffer. This is a bit different from the case of mid- batch uploads which require us to shadow the whole resource (because later draws in an earlier tile happen before earlier draws in a later tile). Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-12-177-63/+334
| | | | Signed-off-by: Rob Clark <[email protected]>
* anv: Remove unused variable.Bas Nieuwenhuizen2017-12-171-2/+0
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* radeonsi: don't call force_dcc_off for buffersMarek Olšák2017-12-161-1/+1
| | | | | | | | This was undefined yet harmless behavior in LLVM. Not anymore - it causes a hang now. Cc: 17.3 <[email protected]> Tested-by: Michel Dänzer <[email protected]>
* isl: Don't require VALIGN_2 for R32G32B32_FLOAT on Haswell.Kenneth Graunke2017-12-151-1/+3
| | | | | | | | | | | | | | According to the RENDER_SURFACE_STATE internal documentation, the R32G32B32_FLOAT restriction is marked "IVB" only. We choose to apply it to Ivybridge and Baytrail, but not Haswell. Apparently fixes KHR-GL46.texture_size_promotion.functional on Haswell. Changes these tests from crashing to skipping on Haswell: - KHR-GL46.direct_state_access.textures_storage_multisample_2d_rgb32f - KHR-GL46.direct_state_access.textures_storage_multisample_3d_rgb32f Reviewed-by: Jason Ekstrand <[email protected]>
* radeon/uvd: add and manage render picture listBoyuan Zhang2017-12-151-4/+25
| | | | | | | | | | | | | | | | Create a list in decoder to store all render picture buffer pointers that currently being used in reference picture lists. During get message buffer call, check each pointer in render_pic_list[] within given pic->ref[] list, remove pointer that no longer being used by pic->ref[]. Then add current render surface pointer to the render_pic_list[] and assign the associated index to result.curr_idx. As a result, result.curr_idx will have the correct index to represent the current render picture, instead of the previous increamenting values. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: add and manage render picture listBoyuan Zhang2017-12-151-4/+24
| | | | | | | | | | | | | | | | Create a list in decoder to store all render picture buffer pointers that currently being used in reference picture lists. During get message buffer call, check each pointer in render_pic_list[] within given pic->ref[] list, remove pointer that no longer being used by pic->ref[]. Then add current render surface pointer to the render_pic_list[] and assign the associated index to result.curr_idx. As a result, result.curr_idx will have the correct index to represent the current render picture, instead of the previous increamenting values. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl: remove is idr flagBoyuan Zhang2017-12-151-1/+0
| | | | | | | Remove is_idr flag since not being used anymore. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: directly use idr pic flagBoyuan Zhang2017-12-151-5/+3
| | | | | | | Remove is_idr flag, and use idr_pic_flag provided by vaapi directly Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: determine idr by pic typeBoyuan Zhang2017-12-151-1/+1
| | | | | | | | | Vaapi encode interface provides idr frame flags, where omx interface doesn't. Therefore, change to use picture type to determine idr frame, which will work for both interfaces. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: determine idr by pic typeBoyuan Zhang2017-12-151-1/+1
| | | | | | | | | | Vaapi encode interface provides idr frame flags, where omx interface doesn't. Therefore, change to use picture type to determine idr frame, which will work for both interfaces. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* util: scons: wire up the sha1 testEmil Velikov2017-12-151-0/+7
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Andres Gomez <[email protected]>
* swr/rast: Move more RTAI handling out of binnerTim Rowley2017-12-152-12/+2
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: EXTRACT2 changed from vextract/vinsert to vshuffleTim Rowley2017-12-153-61/+32
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Fix cache of API thread event managerTim Rowley2017-12-151-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Replace VPSRL with LSHRTim Rowley2017-12-154-41/+4
| | | | | | | | Replace use of x86 intrinsic with general llvm IR instruction. Generates the same final assembly. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Rework thread binding parameters for machine partitioningTim Rowley2017-12-157-88/+322
| | | | | | | | | | | | | Add BASE_NUMA_NODE, BASE_CORE, BASE_THREAD parameters to SwrCreateContext. Add optional SWR_API_THREADING_INFO parameter to SwrCreateContext to control reservation of API threads. Add SwrBindApiThread() function to allow binding of API threads to reserved HW threads. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Pull of RTAI gather & offset out of clip/bin codeTim Rowley2017-12-157-146/+203
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Remove no-op VBROADCAST of vIDTim Rowley2017-12-151-2/+2
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 Fetch - Fully widen 32-bit integer vertex componentsTim Rowley2017-12-154-17/+109
| | | | | | Also widen the 16-bit a 8-bit integer vertex component gathers to SIMD16. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Replace INSERT2 vextract/vinsert with JOIN2 vshuffleTim Rowley2017-12-153-105/+30
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 Fetch - Fully widen 16-bit float vertex componentsTim Rowley2017-12-151-7/+48
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 Fetch - Fully widen 32-bit float vertex componentsTim Rowley2017-12-154-32/+194
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Pass prim to ClipSimdTim Rowley2017-12-151-5/+5
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Pull most of the VPAI manipulation out of the binner/clipperTim Rowley2017-12-157-158/+177
| | | | | | Move out of binner/clipper; hand them down from the frontend code instead. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Move GatherScissors to headerTim Rowley2017-12-152-127/+127
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Rewrite Shuffle8bpcGatherd using shuffleTim Rowley2017-12-151-182/+62
| | | | | | Ease future code maintenance, prepare for folding simd8 and simd16 versions. Reviewed-by: Bruce Cherniak <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 12:32:15 +0000