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* gallium/format: add support for X24S8 and S8X24 formats.Dave Airlie2010-10-136-0/+107
| | | | | | these formats are needed for hw that can sample and write stencil values. Signed-off-by: Dave Airlie <[email protected]>
* gallium/tgsi: add support for stencil writes.Dave Airlie2010-10-137-8/+28
| | | | | | this adds the capability + a stencil semantic id, + tgsi scan support. Signed-off-by: Dave Airlie <[email protected]>
* i965: Don't rebase the index buffer to min 0 if any arrays are in VBOs.Eric Anholt2010-10-124-11/+15
| | | | | | | | | There was a check to only do the rebase if we didn't have everything in VBOs, but nexuiz apparently hands us a mix of VBOs and arrays, resulting in blocking on the GPU to do a rebase. Improves nexuiz 800x600, high-settings performance on my Ironlake 41% (+/- 1.3%), from 14.0fps to 19.7fps.
* intel: Allow CopyTexSubImage to InternalFormat 3/4 textures, like RGB/RGBA.Eric Anholt2010-10-121-0/+2
| | | | | | The format selection of the CopyTexSubImage is pretty bogus still, but this at least avoids software fallbacks in nexuiz, bringing performance from 7.5fps to 12.8fps on my machine.
* i965: Fix missing "break;" in i2b/f2b, and missing AND of CMP result.Eric Anholt2010-10-121-2/+3
| | | | Fixes glsl-fs-i2b.
* glsl: Fix incorrect assertionIan Romanick2010-10-121-1/+1
| | | | | | | This assertion was added in commit f1c1ee11, but it did not notice that the array is accessed with 'size-1' instead of 'size'. As a result, the assertion was off by one. This caused failures in at least glsl-orangebook-ch06-bump.
* mesa: Validate assembly shaders when GLSL shaders are usedIan Romanick2010-10-121-12/+40
| | | | | | | | | | If an GLSL shader is used that does not provide all stages and assembly shaders are provided for the missing stages, validate the assembly shaders. Fixes bugzilla #30787 and piglit tests glsl-invalid-asm0[12]. NOTE: this is a candidate for the 7.9 branch.
* llvmpipe: make sure intrinsics code is guarded with PIPE_ARCH_SSEKeith Whitwell2010-10-121-40/+42
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* st/xorg: Fix typoThomas Hellstrom2010-10-121-1/+1
| | | | | | Pointed out by Jakob Bornecrantz. Signed-off-by: Thomas Hellstrom <[email protected]>
* ir_to_mesa: assorted clean-ups, const qualifiers, new commentsBrian Paul2010-10-121-14/+45
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* gallivm: Name anonymous union.José Fonseca2010-10-122-7/+7
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* st/xlib: add some commentsBrian Paul2010-10-121-0/+8
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* glsl2: fix signed/unsigned comparison warningBrian Paul2010-10-121-1/+1
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* llmvpipe: improve mm_mullo_epi32José Fonseca2010-10-121-4/+3
| | | | | Apply Jose's suggestions for a small but measurable improvement in isosurf.
* st/xorg: Don't try to remove invalid fbsThomas Hellstrom2010-10-121-3/+5
| | | | Signed-off-by: Thomas Hellstrom <[email protected]>
* xorg/vmwgfx: Don't hide HW cursors when updating themThomas Hellstrom2010-10-121-0/+1
| | | | | | Gets rid of annoying cursor flicker Signed-off-by: Thomas Hellstrom <[email protected]>
* st/xorg: Add a customizer option to get rid of annoying cursor update flickerThomas Hellstrom2010-10-123-1/+12
| | | | Signed-off-by: Thomas Hellstrom <[email protected]>
* xorg/vmwgfx: Make vmwarectrl work also on 64-bit serversThomas Hellstrom2010-10-121-0/+1
| | | | Signed-off-by: Thomas Hellstrom <[email protected]>
* st/xorg: Don't try to use option values before processing optionsThomas Hellstrom2010-10-121-13/+13
| | | | Signed-off-by: Thomas Hellstrom <[email protected]>
* Revert "llvmpipe: try to keep plane c values small"Keith Whitwell2010-10-122-24/+17
| | | | | | | This reverts commit 9773722c2b09d5f0615a47cecf4347859474dc56. Looks like there are some floor/rounding issues here that need to be better understood.
* gallivm: don't branch on KILLs near end of shaderKeith Whitwell2010-10-121-10/+47
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* r600g: add missing file to sconscriptKeith Whitwell2010-10-121-0/+1
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* gallium: move sse intrinsics debug helpers to u_sse.hKeith Whitwell2010-10-123-117/+79
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* llvmpipe: Fix MSVC build.José Fonseca2010-10-121-18/+18
| | | | MSVC doesn't accept more than 3 __m128i arguments.
* llvmpipe: fix typo in last commitKeith Whitwell2010-10-121-2/+2
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* llvmpipe: try to keep plane c values smallKeith Whitwell2010-10-122-17/+24
| | | | Avoid accumulating more and more fixed point bits.
* llvmpipe: add debug helpers for epi32 etcKeith Whitwell2010-10-121-0/+115
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* llvmpipe: try to do more of rast_tri_3_16 with intrinsicsKeith Whitwell2010-10-122-9/+271
| | | | | | | | There was actually a large quantity of scalar code in these functions previously. This tries to move more into intrinsics. Introduce an sse2 mm_mullo_epi32 replacement to avoid sse4 dependency in the new rasterization code.
* llvmpipe: Do not dispose the execution engine.José Fonseca2010-10-121-3/+0
| | | | The engine is a global owned by gallivm module.
* nouveau: Get larger push buffers.Francisco Jerez2010-10-123-3/+3
| | | | | Useful to amortize the command submission/reloc overhead (e.g. etracer goes from 72 to 109 FPS on nv4b).
* dri/nouveau: Initialize tile_flags when allocating a render target.Francisco Jerez2010-10-122-6/+14
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* r600g: fix typo in vertex sampling on r600Dave Airlie2010-10-121-1/+1
| | | | | | fixes https://bugs.freedesktop.org/show_bug.cgi?id=30771 Reported-by: Kevin DeKorte
* i965: Always use the new FS backend on gen6.Eric Anholt2010-10-111-2/+7
| | | | | | | | | | It's now much more correct for gen6 than the old backend, with just 2 regressions I've found (one of which is common with pre-gen6 and will be fixed by an array splitting IR pass). This does leave the old Mesa IR backend getting used still when we don't have GLSL IR, but the plan is to get GLSL IR input to the driver for the ARB programs and fixed function by the next release.
* i965: Fix gen6 pixel_[xy] setup to avoid mixing int and float src operands.Eric Anholt2010-10-111-6/+15
| | | | | | | | | | | | | Pre-gen6, you could mix int and float just fine. Now, you get goofy results. Fixes: glsl-arb-fragment-coord-conventions glsl-fs-fragcoord glsl-fs-if-greater glsl-fs-if-greater-equal glsl-fs-if-less glsl-fs-if-less-equal
* i965: Don't compute-to-MRF in gen6 VS math.Eric Anholt2010-10-111-7/+15
| | | | | There was code to do this for pre-gen6 already, this just enables it for gen6 as well.
* i965: Expand uniform args to gen6 math to full registers to get hstride == 1.Eric Anholt2010-10-111-0/+25
| | | | | | | | | | This is a hw requirement in math args. This also is inefficient, as we're calculating the same result 8 times, but then we've been doing that on pre-gen6 as well. If we're doing math on uniforms, though, we'd probably be better served by having some sort of mechanism for precalculating those results into another uniform value to use. Fixes 7 piglit math tests.
* i965: Don't compute-to-MRF in gen6 math instructions.Eric Anholt2010-10-111-0/+16
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* i965: Add a couple of checks for gen6 math instruction limits.Eric Anholt2010-10-111-0/+26
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* i965: Don't consider gen6 math instructions to write to MRFs.Eric Anholt2010-10-111-17/+38
| | | | | This was leftover from the pre-gen6 cleanups. One tests regresses where compute-to-MRF now occurs.
* glsl: Changes in generated file glsl_lexer.cppChad Versace2010-10-111-691/+716
| | | | Signed-off-by: Ian Romanick <[email protected]>
* glsl: Add lexer rules for uint and uvecN (N=2..4)Chad Versace2010-10-111-0/+4
| | | | | | Commit for generated file glsl_lexer.cpp follows this commit. Reviewed-by: Ian Romanick <[email protected]>
* glsl: Add glsl_type::uvecN_type for N=2,3Chad Versace2010-10-112-0/+4
| | | | Reviewed-by: Ian Romanick <[email protected]>
* intel_extensions: Add ability to set GLSL version via environmentChad Versace2010-10-111-1/+18
| | | | | | | | | Add ability to set the GLSL version used by the GLcontext by setting the environment variable INTEL_GLSL_VERSION. For example, env INTEL_GLSL_VERSION=130 prog args If the environment variable is missing, the GLSL versions defaults to 120. Reviewed-by: Ian Romanick <[email protected]>
* r200: revalidate after radeon_update_renderbuffersDaniel Vetter2010-10-113-3/+10
| | | | | | | | | | | | | | | | | By calling radeon_draw_buffers (which sets the necessary flags in radeon->NewGLState) and revalidating if NewGLState is non-zero in r200TclPrimitive. This fixes an assert in libdrm (the color-/ depthbuffer was changed but not yet validated) and and stops the kernel cs checker from complaining about them (when they're too small). Thanks to Mario Kleiner for the hint to call radeon_draw_buffer (instead of my half-broken hack). v2: Also fix the swtcl r200 path. Cc: Mario Kleiner <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
* i965: Compute to MRF in the new FS backend.Eric Anholt2010-10-112-0/+124
| | | | | | This didn't produce a statistically significant performance difference in my demo (n=4) or nexuiz (n=3), but it still seems like a good idea and is recommended by the HW team.
* i965: Give the FB write and texture opcodes the info on base MRF, like math.Eric Anholt2010-10-112-38/+48
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* i965: Give the math opcodes information on base mrf/mrf len.Eric Anholt2010-10-112-12/+57
| | | | This is progress towards enabling a compute-to-MRF pass.
* i965: Move FS backend structures to a header.Eric Anholt2010-10-115-363/+407
| | | | It's time to start splitting some of this up.
* i965: Reduce register interference checks for changed FS_OPCODE_DISCARD.Eric Anholt2010-10-111-5/+2
| | | | | | While I don't know of any performance changes from this (once extra reg available out of 128), it makes the generated asm a lot cleaner looking.
* i965: Split FS_OPCODE_DISCARD into two steps.Eric Anholt2010-10-111-9/+23
| | | | | | Having the single opcode write then read the reg meant that single instruction opcodes had to consider their source regs to interfere with their dest regs.
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