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* i965: Rename BRW_DATAPORT_..._GEN6 messages to GEN6_... for consistency.Kenneth Graunke2011-03-162-9/+9
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* i965: Rename BRW_SAMPLER_MESSAGE_..._GEN5 to GEN5_SAMPLER_MESSAGE.Kenneth Graunke2011-03-163-17/+17
| | | | We already have lots of GEN6_* defines; this seems more consistent.
* svga: Leave any_user_vertex_buffers flag alone.José Fonseca2011-03-162-3/+0
| | | | | It is pointless to change, now that we don't replace user vertex buffer with uploaded copy, per commit 52e598d200108ab9cfc9c9d828bbebdc576e9703.
* svga: Hardcode SVGA_COMBINE_USERBUFFERS to 1.José Fonseca2011-03-165-38/+12
| | | | | | | | The code no longer supports otherwise -- it relies on buffers being uploaded via u_upload_mgr -- so make this clear. Also, there's no need to flush after draws from user buffers, given all user content should have been copied by then.
* mesa: Sort extensions in extension string by year.José Fonseca2011-03-161-216/+278
| | | | | The years were obtained automatically by scraping the first year from the spec text file. They are approximate.
* svga: Use transfer information on buffer transfers.José Fonseca2011-03-162-107/+81
| | | | | | | | Should prevent the assert failure svga_buffer_flush_mapped_range: Assertion `sbuf->map.writing' failed. on nested transfers.
* glsl2: Silence unused added variable gcc warning.José Fonseca2011-03-161-0/+1
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* mesa: Use typecast in BITFIELD64_BIT macro.José Fonseca2011-03-161-5/+1
| | | | | | | | | Unsigned long is 32bit on several platforms (e.g., Windows), yielding 1UL << 32 to be zero. Note that BITFIELD64_BIT result is often assigned to variables of type GLbitfield, instead of GLbitfield64. That's probably wrong and should be addressed in a later change.
* mesa: use BITFIELD64_BIT() macroBrian Paul2011-03-151-2/+2
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* st/mesa: use BITFIELD64_BIT() macro in a few more placesBrian Paul2011-03-153-4/+4
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* glsl: add cast to silence signed/unsigned comparison warningBrian Paul2011-03-151-1/+1
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* mesa: use 1UL for 64-bit unsigned constant for C++Brian Paul2011-03-151-0/+4
| | | | This fixes C++ warnings where BITFIELD64_BIT() is used.
* glsl: Only allow unsized array assignment in an initializerIan Romanick2011-03-151-14/+17
| | | | | | | | | | | It should have been a tip when the spec says "However, implicitly sized arrays cannot be assigned to. Note, this is a rare case that *initializers and assignments appear to have different semantics*." (empahsis mine) Fixes bugzilla #34367. NOTE: This is a candidate for stable release branches.
* i915g: fix braino in the static state reworkDaniel Vetter2011-03-151-1/+2
| | | | | | For mip-map level rendering, both draw offset and size tend to change ... Signed-off-by: Daniel Vetter <[email protected]>
* i915g: implement early zDaniel Vetter2011-03-154-20/+55
| | | | | | v2: Make it actually work. Signed-off-by: Daniel Vetter <[email protected]>
* i915g: split up static stateDaniel Vetter2011-03-155-28/+54
| | | | | | | | Early Z support is set in the DST_VARS command. Hence split up static state emission to avoid reissuing to much on fragment shader changes, especially the costly dst buffer relocations. Signed-off-by: Daniel Vetter <[email protected]>
* i965: Fix alpha testing when there is no color buffer in the FBO.Eric Anholt2011-03-153-0/+13
| | | | | We were alpha testing against an unwritten value, resulting in garbage. (part of) Bug #35073.
* i965: Do our lowering passes before the loop of optimization.Eric Anholt2011-03-151-10/+8
| | | | | | | | The optimization loop won't reinsert noise instructions or quadop vectors, so we were traversing the tree for nothing. Lowering vector indexing was in the loop after do_common_optimization() to avoid the work if it ended up that the index was actually constant, but that has been called already in the core.
* glsl: Skip processing the first function's body in do_dead_functions().Eric Anholt2011-03-151-1/+10
| | | | It can't call anything, so there's no point.
* glsl: Whitespace fixup in opt_dead_functions.cpp.Eric Anholt2011-03-151-106/+108
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* glsl: Skip processing of expression trees in discard simplification.Eric Anholt2011-03-151-0/+10
| | | | It only cares about "if", "loop", and "discard".
* glsl: Reduce processing of expression trees in do_structure_splitting.Eric Anholt2011-03-151-0/+6
| | | | | | Most of the time we don't have a non-uniform struct variable in the shader, so this cuts the time spent in do_structure_splitting during glean texCombine by about 2/3.
* glsl: Skip processing expression trees in do_if_simplification().Eric Anholt2011-03-151-0/+10
| | | | Reduces time spent in this during glean texCombine by about 2/3.
* glsl: Skip processing expression trees in optimize_redundant_jumps()Eric Anholt2011-03-151-0/+9
| | | | Cuts the time spent in this function during glean texCombine by 2/3.
* svga: Tell the host to discard when doing writes without FLUSH_EXPLICIT.José Fonseca2011-03-151-3/+10
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* svga: Update svga_winsys_screen::buffer_map comments.José Fonseca2011-03-151-2/+2
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* svga: Ensure DMA commands are serialized with unsynchronized flag is unset.José Fonseca2011-03-153-19/+113
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* scons: copy hash_table.c, symbol_table.c to glsl directoryJose Fonseca2011-03-151-2/+7
| | | | | | | | This fixes an issue where the .obj files wound up in the src/ directory rather than the build/ directory. That prevented combined 32-bit and 64-bit builds from working. Signed-off-by: Brian Paul <[email protected]>
* mesa: fix scons buildMarek Olšák2011-03-151-1/+1
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* r300g: implement the texture barrierMarek Olšák2011-03-151-0/+10
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* gallium: add texture barrier support to the interface and st/mesa (v2)Marek Olšák2011-03-158-0/+120
| | | | v2: change the gallium entry point to texture_barrier.
* mesa: add display list support for NV_texture_barrierMarek Olšák2011-03-151-0/+22
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* mesa: regenerate glapi filesMarek Olšák2011-03-1511-2431/+2500
| | | | | Be sure to type "make clean" after this commit, otherwise your binaries will segfault.
* mesa: add NV_texture_barrierMarek Olšák2011-03-1512-0/+130
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* gallium/util: Use PIPE_TRANSFER_DISCARD_RANGE in pipe_buffer_write.Mathias Fröhlich2011-03-151-0/+2
| | | | | | | | Additionally, to discarding the whole buffer, use PIPE_TRANSFER_DISCARD_RANGE in pipe_buffer_write when the write covers only part of the buffer. Signed-off-by: Mathias Fröhlich <[email protected]>
* st/mesa: Make use of the new PIPE_TRANSFER_DISCARD_* for buffer object.Mathias Fröhlich2011-03-151-5/+9
| | | | | | | | In memory mapping buffer objects make use of PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE and PIPE_TRANSFER_DISCARD_RANGE when appropriate. Signed-off-by: Mathias Fröhlich <[email protected]>
* glx: add ARB_create_context functions/ops to glx xmlDave Airlie2011-03-151-0/+14
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* r600g: FLT_TO_INT_FLOOR and FLT_TO_INT_RPI are vector-only instructions on ↵Henri Verbeet2011-03-151-3/+6
| | | | | | Evergreen. Signed-off-by: Henri Verbeet <[email protected]>
* r600g: fix logic error in 028987c80362eddd39176628486a456b076f0427Alex Deucher2011-03-141-1/+1
| | | | | | Spotted by Henri on IRC. Signed-off-by: Alex Deucher <[email protected]>
* r600g: don't set per-MRT blend bits on R600Alex Deucher2011-03-141-5/+10
| | | | | | | | | It doesn't support them. Also, we shouldn't be emitting CB_BLENDx_CONTROL on R600 as the regs don't exist there, but I'm not sure of the best way to deal with this in the current r600 winsys. Signed-off-by: Alex Deucher <[email protected]>
* r600g: Original R600 does not support per-MRT blendsAlex Deucher2011-03-141-2/+11
| | | | | | Only rv6xx+ support them. Signed-off-by: Alex Deucher <[email protected]>
* r600g: emit SURFACE_BASE_UPDATE packet on rv6xxAlex Deucher2011-03-142-2/+25
| | | | | | | | This packet is required when updating the DB, CB, or STRMOUT base addresses on rv6xx for the surface sync logic to work correctly. Signed-off-by: Alex Deucher <[email protected]>
* r600g: Properly update MULTIWRITE_ENABLE in r600_pipe_shader_ps().Henri Verbeet2011-03-142-8/+7
| | | | | | | This sort of worked because blend state setup cleared MULTIWRITE_ENABLE again, but that's not something we want to depend on. Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Fix the DB_SHADER_CONTROL mask in create_ds_state().Henri Verbeet2011-03-142-10/+8
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Properly update DB_SHADER_CONTROL in evergreen_pipe_shader_ps().Henri Verbeet2011-03-141-18/+14
| | | | | | | Disable Z_EXPORT / STENCIL_EXPORT / KILL_ENABLE again if a shader doesn't use those. This is similar to 0a6f09a76a416b8672e149c520aa5bef33174223. Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Move fetch shader register setup to r600_state.c / evergreen_state.c.Henri Verbeet2011-03-146-31/+32
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Move r600_pipe_shader_ps() to r600_state.c.Henri Verbeet2011-03-143-95/+97
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Move r600_pipe_shader_vs() to r600_state.c.Henri Verbeet2011-03-143-49/+49
| | | | | | | | The idea behind this is that anything touching registers should be in r600_state.c or evergreen_state.c. This is also consistent with evergreen_pipe_shader_vs(). Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Evergreen add support for log opcode.Rafael Monica2011-03-141-1/+1
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* autoconf/make: Don't specify individual llvm libraries.José Fonseca2011-03-142-4/+4
| | | | | | | We need more and more of these, and it is difficult and prone to version incompatability issues trying to single out every one of them. This mimicks what was done in SCons.