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* vl/dri3: get Makefile properlyLeo Liu2016-06-103-5/+10
| | | | | | | | | | | | | | From original commit, the macro "if HAVE_DRI3" was in Makefile.sources, this file is shared with SCons, SCons is not able to parse this marco, the SCons build failed. Jose quickly gave two approaches and quick fix with his second approach, thanks Jose for the solutions and fixes. This patch is Jose's first approach, and it's more proper, because the dri3 c file should not be included to build when DRI3 is not enabled. Signed-off-by: Leo Liu <[email protected]> Acked-by: Emil Velikov <[email protected]> Cc: "12.0" <[email protected]>
* gallivm: Never emit llvm.fmuladd on LLVM 3.3.Jose Fonseca2016-06-102-1/+7
| | | | | | | | Besides the old JIT bug, it seems the X86 backend on LLVM 3.3 doesn't handle llvm.fmuladd and instead it fall backs to a C function. Which in turn causes a segfault on Windows. Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: Use llvm.fmuladd.*.Jose Fonseca2016-06-107-68/+98
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* util,gallivm: Explicitly enable/disable fma attribute.Jose Fonseca2016-06-104-0/+13
| | | | | | | | | | As suggested by Roland Scheidegger. Use the same logic as f16c, since fma requires VEX encoding. But disable FMA on LLVM 3.3 without MCJIT. Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: Reinitialize all descriptors in CE preamble.Bas Nieuwenhuizen2016-06-103-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | This fixes a problem with the CE preamble and restoring only stuff in the preamble when needed. To illustrate suppose we have two graphics IB's 1 and 2, which are submitted in that order. Furthermore suppose IB 1 does not use CE ram, but IB 2 does, and we have a context switch at the start of IB 1, but not between IB 1 and IB 2. The old code put the CE RAM loads in the preamble of IB 2. As the preamble of IB 1 does not have the loads and the preamble of IB 2 does not get executed, the old values are not load into CE RAM. Fix this by always restoring the entire CE RAM. v2: - Just load all descriptor set buffers instead of load and store the entire CE RAM. - Leave the ce_ram_dirty tracking in place for the non-preamble case. v3: - Fixed parameter alignment. - Rebased to master (Nicolai's descriptor series). Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: Wrap extensions.h declarations with extern "C".Jose Fonseca2016-06-101-0/+8
| | | | | | | This should fix the MSVC linker failures that arose with commit 5e2d25894b962aae9158261897e13843377e3b95. Trivial.
* st/mesa: fix type confusion with reladdrsIlia Mirkin2016-06-091-5/+5
| | | | | | | | | | | The reality is that this doesn't matter, because we manually emit the ARL to the sampler reladdr, and those arguments don't get an extra load later, so it's effectively just a boolean. However having the types be wrong is confusing and could trigger very odd bugs should usage change down the line. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* glsl/ir: remove TABs in ir_constant_expression.cppDave Airlie2016-06-101-535/+535
| | | | | | | | Adding 64-bit integers support was going to make this file worse, just remove the tabs from it now. Acked-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965/gen9: Don't change halign and valign to fit in fast copy blitAnuj Phogat2016-06-091-4/+2
| | | | | | | | | An update in graphics specs has deleted the halign and valign fields from XY_FAST_COPY_BLT command. See mesa commit 97f0f91. Cc: Ben Widawsky <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* mesa: Add a helper function for shared code in get_tex_rgba_{un}compressedAnuj Phogat2016-06-091-45/+38
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Let compute shaders work in compatibility profilesSamuel Pitoiset2016-06-091-1/+1
| | | | | | | | | | The extension is already advertised in compatibility profile, but the _mesa_has_compute_shaders only returns true in core profile. If we advertise it, we should allow it to work. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* swr: implement clipPlanes/clipVertex/clipDistance/cullDistanceTim Rowley2016-06-096-3/+95
| | | | | | | | | | | | | | v2: only load the clip vertex once v3: fix clip enable logic, add cullDistance v4: remove duplicate fields in vs jit key, fix test of clip fixup needed v5: fix clipdistance linkage for slot!=0,4 v6: support clip+cull; passes most piglit clip (failures understood) Reviewed-by: Bruce Cherniak <[email protected]>
* glx: fix crash with bad fbconfigDaniel Czarnowski2016-06-091-0/+23
| | | | | | | | | | | | | | | | | | | GLX documentation states: glXCreateNewContext can generate the following errors: (...) GLXBadFBConfig if config is not a valid GLXFBConfig Function checks if the given config is a valid config and sets proper error code. Fixes currently crashing glx-fbconfig-bad Piglit test. v2: coding style cleanups (Emil, Topi) use DefaultScreen macro (Emil) Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Cc: "11.2" <[email protected]>
* st/vdpau: implement luma keyingNayan Deshmukh2016-06-092-12/+39
| | | | | Signed-off-by: Nayan Deshmukh <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl: Apply luma key filter before CSC conversionNayan Deshmukh2016-06-097-20/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apply the luma key filter to the YCbCr values during the CSC conversion in video buffer shader. The initial values of max and min luma are set to opposite values to disable the filter initially and will be set when enabling it. Add extra parmeters min and max luma for the luma key filter in vl_compositor_set_csc_matrix in va, xvmc. Setting them to opposite value 1.f and 0.f respectively won't effect the CSC conversion v2: -Squash 1,2 and 3 into one patch to avoid breaking build of other components. (Christian) -use ureg_swizzle. (Christian) -change name of the variables. (Christian) v3: -Squash all patches in one to avoid breaking of build. (Emil) -wrap functions properly. (Emil) -use 0.0f and 1.0f instead of 0.f and 1.f respectively. (Emil) v4: -Divide it in two patches one which introduces the functionality and assigs dummy values to the changed functions and second which implements the lumakey filter. (Christian) -use ureg_scalar instead ureg_swizzle. (Christian) Signed-off-by: Nayan Deshmukh <[email protected]> Reviewed-by: Christian König <[email protected]>
* i965: Emit surface states for extra planes prior to gen8Jason Ekstrand2016-06-082-0/+18
| | | | | | | | | | When Kristian implemented GL_TEXTURE_EXTERNAL_OES, he hooked it up for gen8 but not for gen7 or earlier. It all works, we just need to emit the states for the extra planes. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Cc: "12.0" <[email protected]>
* virgl: fix checking fencesMarc-André Lureau2016-06-092-2/+2
| | | | | | | | | | | | | | When calling virgl_fence_wait() with timeout=0, virgl_{drm,vtest}_resource_is_busy() is called. However, it returns TRUE for a busy resource, whereace virgl_fence_wait() should return TRUE for a completed (non-busy) resource. This fixes running supertuxkart in a VM (I could not reproduce locally with vtest though there is a similar fix) Signed-off-by: Marc-André Lureau <[email protected]> Cc: "11.1 11.2 12.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glsl/types: rename is_dual_slot_double to is_dual_slot_64bit.Dave Airlie2016-06-095-10/+10
| | | | | | | In the future int64 support will have the same requirements. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st/glsl_to_tgsi: move to checking 64-bitness instead of doubleDave Airlie2016-06-091-16/+14
| | | | | | | | This uses the new types interfaces to check for 64-bit types, as futureproofing against int64 support. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st/glsl_to_tgsi: use enum glsl_base_type instead of unsignedDave Airlie2016-06-091-12/+12
| | | | | | | | This is just some better type safety that I noticed while working on 64-bit integer support. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: use new 64-bit checks instead of explicit double checks.Dave Airlie2016-06-092-5/+5
| | | | | | | This just moves to the new interfaces in advance of int64. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glsl/link_varyings: switch to 64bit check instead of double.Dave Airlie2016-06-092-3/+3
| | | | | | | This is prep work for int64 support. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glsl: use new interfaces for 64-bit checks.Dave Airlie2016-06-095-14/+14
| | | | | | | | This is just prep work for int64 support, changing places where 64-bit matters no doubles. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* compiler: use 64bit check for sizing instead of double check.Dave Airlie2016-06-091-5/+5
| | | | | | | This just moves code to the new check in advance of int64 support. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* compiler/types: add 64-bitness queries.Dave Airlie2016-06-091-0/+13
| | | | | | | | | | This adds an inline and type query for if a type is 64-bit. Fow now this is equivalent to double, but int64 will change this. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glapi/glx: Add overflow checks to the client-side indirect codeAdam Jackson2016-06-081-0/+9
| | | | | | | | | | | | | Coverity complains that the computed sizes can lead to negative lengths passed to memcpy. If that happens we've been handed invalid arguments anyway, so just bomb out. The funky "0%s" is because the size string for the variable-length part of the request is of the form "+ safe_pad() ...", and a unary + would coerce the result to always be positive, defeating the overflow check. Signed-off-by: Adam Jackson <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* radeonsi: improve the computation and comment of scratch_wavesMarek Olšák2016-06-081-4/+18
| | | | | | 2% isn't much. If you think the number should be decreased, please speak up. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: print the number of spilled VGPRsMarek Olšák2016-06-081-3/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove dead code creating LLVMTargetMachineMarek Olšák2016-06-083-27/+1
| | | | | | | | This was for some old unsupported LLVM version. Only si_create_context creates the target machine now. r600g doesn't use this function. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't enable scratch just for SGPR spillsMarek Olšák2016-06-081-2/+17
| | | | | | | | | Diff from shader-db: Scratch: 3221504 -> 17408 (-99.46 %) bytes per wave v2: add "break;" Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: try not to compile compute shader on the first useMarek Olšák2016-06-081-0/+1
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* Revert "radeonsi: allow direct hw MSAA resolve for scanout surfaces"Marek Olšák2016-06-081-0/+1
| | | | | | This reverts commit ffd54d1936fcd07424265b780e1d049222a01e94. No, it doesn't work. The test case is "glxgears -samples 2".
* st/mesa: directly compute level=0 texture size in st_finalize_textureNicolai Hähnle2016-06-085-53/+48
| | | | | | | | | | | | | | | | | | | | | | | | The width0/height0/depth0 on stObj may not have been set at this point. Observed in a trace that set up levels 2..9 of a 2d texture, and set the base level to 2, with height 1. This made the guess logic always bail. Originally investigated by Ilia Mirkin, this patch gets rid of the somewhat redundant storage of width0/height0/depth0 and makes sure we always compute pipe texture sizes that are compatible with the base level image of the GL texture. Fixes the gl-1.2-texture-base-level piglit test provided by Brian Paul. v2: - try to re-use an existing pipe texture when possible - handle a corner case where the base level is not level 0 and it is of size 1x1x1 v3: - ptHeight = ptWidth in cube map 1x1 case (suggested by Brian) Cc: "12.0" <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* glsl: stop allocating memory for SSBOs and builtinsTimothy Arceri2016-06-081-7/+13
| | | | | | | | | This just stops counting and assigning a storage location for these uniforms, the count is only used to create the uniform storage. These uniform types don't use this storage. Reviewed-by: Dave Airlie <[email protected]>
* st/mesa: use buffer usage history to set dirty flags for revalidationIlia Mirkin2016-06-071-2/+13
| | | | | | | | | | We were previously unconditionally doing this for arrays and ubo's, and ignoring texture/storage/atomic buffers. Instead use the usage history to determine which atoms need to be revalidated. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Cc: "12.0" <[email protected]>
* i965: Integrate precise trig into configuration infrastructureGurchetan Singh2016-06-074-2/+10
| | | | | | | | | | | | | | With this change, to enable precise SIN and COS instructions on Intel hardware, one can put <option name="precise_trig" value="true"/> in the proper drirc file. V2: Make option name more generic Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Stephane Marchesin <[email protected]>
* radeonsi: re-enable PBO ReadPixels accelerationMarek Olšák2016-06-081-3/+6
| | | | | | disabled by 4f1cccf570112f93265a4cace504eb763fa8f73e Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: allow MSAA resolving into a texture that has DCC enabledMarek Olšák2016-06-082-4/+23
| | | | | | | | Since DCC is enabled almost everywhere now, it's important not to disable this fast path. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium/radeon: move DCC clearing into a separate functionMarek Olšák2016-06-082-5/+19
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: allow direct hw MSAA resolve for scanout surfacesMarek Olšák2016-06-081-1/+0
| | | | | | | No idea why this was disabled, but it works fine. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: don't allocate DCC for the temporary MSAA resolve surfaceMarek Olšák2016-06-083-2/+5
| | | | | | | Allocating it has no effect, but it adds overhead (useless DCC clear). Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: don't enable DCC in the sampler if first_level doesn't have itMarek Olšák2016-06-083-7/+21
| | | | | | | | If first_level > 0 and DCC is disabled for that level, let's skip DCC reads entirely. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* winsys/amdgpu: enable DCC for mipmapped texturesMarek Olšák2016-06-083-9/+31
| | | | | | | | Also add dcc_fast_clear_size for clearing only the necessary subset of DCC. For no AA, it's equal to the size of the whole DCC level. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium/radeon: don't disable DCC because of SDMAMarek Olšák2016-06-081-20/+3
| | | | | | | | We want to keep DCC enabled to save bandwidth. It was a bad idea to disable it here. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: don't flag renderbuffer feedback loop if DCC has just been disabledMarek Olšák2016-06-081-2/+4
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: add per-level dcc_enabled flagsMarek Olšák2016-06-086-11/+24
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: compute DCC register parameters in si_emit_framebuffer_stateMarek Olšák2016-06-084-14/+12
| | | | | | | | This will get more complicated with mipmapped DCC or when DCC is enabled after allocation. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium/radeon: add an assertion checking the validity of PIPE_BIND_SCANOUTMarek Olšák2016-06-081-3/+10
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium/radeon: don't allocate DCC for non-renderable texture formatsMarek Olšák2016-06-083-0/+7
| | | | | | | | | | | R9G9B9E5 is the only uncompressed one hopefully. This fixes incorrect rendering not discovered (due to a lack of tests) until DCC mipmapping was enabled. Cc: 11.1 11.2 12.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: enable WQM in PS prolog when neededNicolai Hähnle2016-06-072-0/+10
| | | | | | | | | | | | WQM is needed when the PS prolog computes a VGPR that is consumed by a shader with (implicit or explicit) derivatives. Depends on http://reviews.llvm.org/D20839 / LLVM r272063 for this to be effective (otherwise it's just a no-op). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95130 Cc: 12.0 <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
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