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* automake: merge gallium/state_trackers/Makefile into gallium/MakefileEmil Velikov2014-08-134-68/+49
| | | | | | | | | | One makefile less, with the potential of further compacting the automake build. v2: Rebase on top of vc4 changes. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* automake: compact gallium/drivers and gallium/winsys makefilesEmil Velikov2014-08-135-181/+106
| | | | | | | | | | | | Rather than having two separate almost empty and identical makefiles, compact them thus improving the configure and build time. Additionally this makes the automake build symmetrical to the scons and android one. v2: Rebase on top of vc4, compact drivers + winsys on a single line. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* android: egl/main: add/enable freedrenoEmil Velikov2014-08-132-0/+9
| | | | | | | | | | For all everyone willing to give the freedreno driver a go they can now build it under Android. Cc: "10.1 10.2" <[email protected]> Cc: Rob Clark <[email protected]> Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]>
* android: gallium/freedreno: add preliminary buildEmil Velikov2014-08-134-2/+88
| | | | | | | | | | | | | | | | | | For all the people interested in testing the freedreno driver on their Android devices. The next commit will hook these up within the libEGL driver (via the gallium-egl backend). There may be some rough edges but those can be sorted when a willing builder/tester comes along. v2: - s/freefreno/freedreno/. Spotted by Matt Turner. - Use the installed libdrm headers. Cc: "10.1 10.2" <[email protected]> Cc: Rob Clark <[email protected]> Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]>
* automake: gallium/freedreno: drop spurious include dirsEmil Velikov2014-08-132-4/+2
| | | | | | | | | | | Rather than including two extra folders only for two headers, just prefix the headers and be done with it. Cc: "10.1 10.2" <[email protected]> Cc: Rob Clark <[email protected]> Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* android: egl/main: resolve radeon linking issuesPaulo Sergio Travaglia2014-08-131-4/+9
| | | | | | | | | | | | | - link against libdrm_radeon - link the r600 driver against libstlport - linkin the newly added libmesa_pipe_radeon library required by r600 and radeonsi drivers v2: Include pipe_radeon after pipe_r600/radeonsi. Cc: "10.1 10.2" <[email protected]> [Emil Velikov] Split up and add commit message. Signed-off-by: Emil Velikov <[email protected]>
* android: gallium/radeon: attempt to fix the android buildPaulo Sergio Travaglia2014-08-136-7/+45
| | | | | | | | | | | - include the correct folders - add a new buildscript for the common radeon folder v2: Use the installed libdrm headers over the DRM_TOP ones. Cc: "10.1 10.2" <[email protected]> [Emil Velikov] Split up and add commit message. Signed-off-by: Emil Velikov <[email protected]>
* android: egl/main: fixup the nouveau buildEmil Velikov2014-08-131-6/+2
| | | | | | | | | For a while the nouveau pipe driver has been a static library and it has been using STL for even longer. Correct add the link and cleanup the gallium_DRIVERS. Cc: "10.1 10.2" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* android: gallium/nouveau: fix include folders, link against libstlportEmil Velikov2014-08-132-8/+6
| | | | | | | | | | | nouveau uses STL for a while now thus we need to include external/stlport/libstlport.mk in order to get the build at least partially working. v2: Use the installed libdrm headers over the DRM_TOP ones. Cc: "10.1 10.2" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* egl/main: Bring in the Makefile.sourcesEmil Velikov2014-08-134-75/+47
| | | | | | | | Rather than having the sources list duplicated across all three build systems, define it once and use it whenever needed. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nvc0: add BPTC format supportIlia Mirkin2014-08-123-2/+9
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* mesa/st: add BPTC formats, expose ARB_texture_compression_bptcIlia Mirkin2014-08-123-1/+49
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* softpipe,llvmpipe: mark BPTC formats as unsupportedIlia Mirkin2014-08-122-0/+10
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: add basic support for BPTC formatsIlia Mirkin2014-08-129-3/+165
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* docs: add GL4.5 sectionIlia Mirkin2014-08-121-0/+16
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* configure.ac: drop enable_dri check in gallium_gbmEmil Velikov2014-08-121-4/+0
| | | | | | | A while back we've mandated that gbm requires enable_dri, thus this check is no longer required. Signed-off-by: Emil Velikov <[email protected]>
* configure.ac: bail out if building gallium_gbm without gallium_eglEmil Velikov2014-08-121-0/+4
| | | | | | | | The former is the only user of the latter. As such building gbm without egl makes little to no sense. Cc: "10.2" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* st/dri: define GALLIUM_SOFTPIPE when building kms_swrastEmil Velikov2014-08-123-3/+9
| | | | | | | | | | | | | | | To avoid unresolved symbols in the DRI modules with earlier commit we wrapped the innards of dri_kms_init_screen() in a DRI_TARGET/GALLIUM_SOFTPIPE ifdef. At the same time we forgot to adds the defines to the st/dri build systems, breaking kms_swrast and gnome-continuous. Drop the DRI_TARGET define, we're already in st/DRI. Reported-by: Jasper St. Pierre <[email protected]> Reported-by: Vadim Rutkovsky <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* configure: Fix --enable-XX-bit flags by moving LT_INIT where it shouldAlexandre Demers2014-08-121-3/+8
| | | | | | | | | | | | | | Moving LT_INIT after setting completely (AM_)C(XX)FLAGS and LDFLAGS. LT_INIT needs them as they are expected to be used all along the compilation when the macro runs its tests to determine among other things the host type. For info, see http://www.gnu.org/software/libtool/manual/html_node/LT_005fINIT.html Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50754 Signed-off-by: Alexandre Demers <[email protected]> Tested-by: Tapani Palli <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* c11/threads: correct assertionEmil Velikov2014-08-121-1/+1
| | | | | | | | | | We should assert when either the function or the flag pointer is null or we'll end up with a null reference a few lines later. Currently unused by mesa thus it has gone unnoticed. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* docs: now distributing the GL/glcorearb.h headerBrian Paul2014-08-121-0/+1
| | | | Reviewed-by: Matt Turner <[email protected]>
* mesa: pull Khronos glcorearb.h header into include/GL/Brian Paul2014-08-121-0/+3589
| | | | | | | Apps that only want to use core functionality should #include this header. This version covers everything up to OpenGL 4.5. Reviewed-by: Matt Turner <[email protected]>
* vc4: Drop the dump_fbo() routine.Eric Anholt2014-08-121-50/+0
| | | | | Now that eglkms is working, and some tests are working under PIGLIT_PLATFORM=gbm, I don't think I need this any more.
* vc4: Claim the GL 2.1 minimum for 3D textures.Eric Anholt2014-08-121-1/+2
| | | | | | | We don't actually do them (or even fake them) currently, but it does get us a bunch of unrelated glean glsl1 tests passing, which previously would error out due to glean assuming the minimums on a 3D texture that 2 of the subtests use.
* vc4: Declare what vertex formats we actually support.Eric Anholt2014-08-121-2/+7
| | | | | We will support more than this eventually, but for now this makes u_vbuf format-convert a few things (32-bit snorm and scaled, doubles) for us.
* vc4: Stash some debug code for format support checks.Eric Anholt2014-08-121-0/+9
| | | | | | This can be useful for looking at context init setup and texture format choices, and there's no reason for the silly retval computation we do if you're not going to have this code (mostly from freedreno) around.
* vc4: Texture format support has nothing to do with VBO format support.Eric Anholt2014-08-121-2/+1
| | | | This was inherited from freedreno, but doesn't apply to us.
* vc4: Fix off-by-one in texture maximum levels.Eric Anholt2014-08-121-1/+1
| | | | It's 2048x2048 that's the max, not 1024x1024.
* vc4: Add support for the FLR opcode.Eric Anholt2014-08-121-0/+18
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* i965: Delete the Gen8 code generators.Kenneth Graunke2014-08-129-4076/+0
| | | | | | | | We now use the brw_eu_emit.c code instead. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Never use the Gen8 code generators.Kenneth Graunke2014-08-123-28/+10
| | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Switch to the EU emit layer for code generation on Broadwell.Kenneth Graunke2014-08-123-3/+3
| | | | | | | | | | | | | Everything should be in place to unify code generation between Gen4-7 and Gen8+. We should be able to drop the Gen8 generators at this point. However, leave them hooked up for a brief moment, for testing and comparison purposes. Set GEN8=1 to use the old Gen8+ code generator paths. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Retype atomics to UD in Gen8 code generation.Kenneth Graunke2014-08-122-4/+8
| | | | | | | | | | Kind of a moot point since we're deleting Gen8 code generation, but this at least helps make it match the Gen4-7 code. It's probably more reasonable than using float. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vp: Use the sampler for pull constant loads on Gen7/7.5.Kenneth Graunke2014-08-121-5/+12
| | | | | | | | | | | | | This improves performance in Trine 2 at 1280x720 (windowed) on "Very High" settings by 30% (in the interactive menu) to 45% (in the forest by the giant frog) on Haswell GT3e. It also now generates the same assembly on Gen7 as it does on Gen8, which always used the sampler for both types. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Drop gen <= 7 assertion in pull constant load handling.Kenneth Graunke2014-08-121-1/+0
| | | | | | | | I don't see any reason for this to exist. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/eu: Set src0 file to IMM on Gen8+ flow control instructions.Kenneth Graunke2014-08-121-9/+36
| | | | | | | | | | | | | | | According to the documentation, we need to set the source 0 register type to IMM for flow control instructinos that have both JIP and UIP. Out of paranoia, just make all flow control instructions use IMM; there's no benefit to using ARF anyway, and it could trouble that's difficult to diagnose. See commit 9584959123b0453cf5313722357e3abb9f736aa7, which did the analogous change in the gen8_generator code. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/eu: Refactor brw_WHILE to share a bit more code on Gen6+.Kenneth Graunke2014-08-121-16/+12
| | | | | | | | | We're going to add a Gen8+ case shortly, which would need to duplicate this code again. Instead, share it. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/eu: Emulate F32TO16 and F16TO32 on Broadwell.Kenneth Graunke2014-08-121-2/+50
| | | | | | | | | | | | | | | | | When we combine the Gen4-7 and Gen8+ generators, we'll need to handle half float packing/unpacking functions somehow. The Gen8+ generator code today just emulates the behavior of the Gen7 F32TO16/F16TO32 instructions, including the align16 mode bugs. Rather than messing with fs_generator/vec4_generator, I decided to just emulate the instructions at the brw_eu_emit.c layer. v2: Change gen >= 7 asserts to gen == 7 (suggested by Chris Forbes). Fix regressions on Haswell in VS tests due to type assertions. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Port Gen8 SET_VERTEX_COUNT handling to vec4_generator.Kenneth Graunke2014-08-121-18/+25
| | | | | | | | | | | | Broadwell requires the number of vertices written by the geometry shader to be specified in a separate register, as part of the terminating message's payload. This also means GS_OPCODE_THREAD_END needs to increment mlen. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Switch to MOV, not OR, for GS_OPCODE_THREAD_END on Gen8.Kenneth Graunke2014-08-121-4/+3
| | | | | | | | Either should work. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Use MOV, not OR, to set URB write channel mask bits.Kenneth Graunke2014-08-121-4/+2
| | | | | | | | | | | | | | g0.5 has nothing of value to contribute to m0.5. In both the VS and GS payload, g0.5 contains the scratch space pointer - which is definitely not of any use. The GS payload also contains FFTID, but the URB write message header doesn't want FFTID. The only reason I used OR was because Eric originally requested it. On Broadwell, I used MOV, and that's worked out fine. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Don't set flag_subreg_nr = 1 on predicated FB write setup.Kenneth Graunke2014-08-121-0/+1
| | | | | | | | | | | | | | | On Haswell, we implement "discard" via predicated SEND messages, using f0.1 instead of f0.0. To accomplish this, we set inst->flag_subreg to 1 on the FS_OPCODE_FB_WRITE. Most instructions using fs_inst::flag_subreg expand to a single assembly instruction. However, FS_OPCODE_FB_WRITE can generate several MOVs for setting up header information. We don't want to set flag_subreg on those, so override the default state back to 0. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/vec4: Respect ir->force_writemask_all in Gen8 code generation.Kenneth Graunke2014-08-121-0/+1
| | | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Cc: "10.2" <[email protected]>
* i965/vec4: Set NoMask for GS_OPCODE_SET_VERTEX_COUNT on Gen8+.Kenneth Graunke2014-08-121-1/+3
| | | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Cc: "10.2" <[email protected]>
* gallium/r300: Fix a link error in the testsJason Ekstrand2014-08-121-1/+1
| | | | | | | | | The link error occurs because the static libraries are linked in the wrong order. This fixes it. Signed-off-by: Jason Ekstrand <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82483 Reviewed-by: Tom Stellard <[email protected]>
* i965: Return NONE from brw_swap_cmod on unknown input.Matt Turner2014-08-123-3/+3
| | | | | | | | Comparing ~0u with a packed enum (i.e., 1 byte) always evaluates to false. Shouldn't gcc warn about this? Reported-by: Connor Abbott <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* docs: Update release notes and GL3.txt for GL_ARB_texture_compression_bptcNeil Roberts2014-08-122-1/+2
| | | | Reviewed-by: Ian Romanick <[email protected]>
* mesa/meta: Support decompressing floating-point formatsNeil Roberts2014-08-122-33/+78
| | | | | | | | | | | | | Previously the Meta implementation of glGetTexImage would fall back to _mesa_get_teximage if the texturing is not using an unsigned normalised format. However in order to support the half-float formats of BPTC textures we can make it render to a floating-point renderbuffer instead. This patch makes decompression_state have two FBOs, one for the GL_RGBA format and one for GL_RGBA32F. If a floating-point texture is encountered it will try setting up a floating-point FBO. It will now also check the status of the FBO and fall back to _mesa_get_teximage if the FBO is not complete. Reviewed-by: Ian Romanick <[email protected]>
* swrast: Enable GL_ARB_texture_compression_bptcNeil Roberts2014-08-121-0/+1
| | | | | | Enables BPTC texture compression on the software rasterizer. Reviewed-by: Ian Romanick <[email protected]>
* i965: Enable the GL_ARB_texture_compression_bptc extensionNeil Roberts2014-08-122-0/+7
| | | | | | | Enables the BPTC extension on Gen>=7 and adds the necessary format mappings to get the right surface type value. Reviewed-by: Ian Romanick <[email protected]>
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