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* freedreno/ir3: add TXL supportIlia Mirkin2014-09-121-1/+3
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add missing put_dstRob Clark2014-09-121-0/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: catch incorrect usage of tmp-dstRob Clark2014-09-121-0/+15
| | | | | | | Each get_dst() should have a matching put_dst(). Add a bit of checking to catch mistakes. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use unsigned comparison for UIFIlia Mirkin2014-09-121-4/+4
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: negate result of USLT/etcIlia Mirkin2014-09-121-8/+15
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add UARL supportIlia Mirkin2014-09-121-2/+4
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: INEG operates on src0, not src1Ilia Mirkin2014-09-121-1/+3
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix FSLT/etc handling to return 0/-1 instead of 0/1.0Ilia Mirkin2014-09-121-4/+8
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: alpha render-target shenanigansRob Clark2014-09-124-2/+34
| | | | | | | | | We need the .w component to end up in .x, since the hw appears to fetch gl_FragColor starting with the .x coordinate regardless of MRT format. As long as we are doing this, we might as well throw out the remaining unneeded components. Signed-off-by: Rob Clark <[email protected]>
* util/u_format: add _is_alpha()Rob Clark2014-09-122-0/+19
| | | | | | | | | Because of render-to-alpha (000x) shenanigans, freedreno needs to do some special handling when rendering to alpha-only formats. And I noticed that while we had _is_luminance(), _is_intensity(), etc, an _is_alpha() helper was missing. So fix that. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: format fixesRob Clark2014-09-123-5/+20
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-09-124-4/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: handle rendering to layer != 0Rob Clark2014-09-121-2/+12
| | | | Signed-off-by: Rob Clark <[email protected]>
* mesa: fix _mesa_free_pipeline_data() use-after-free bugBrian Paul2014-09-121-2/+2
| | | | | | | | | | | | | Unreference the ctx->_Shader object before we delete all the pipeline objects in the hash table. Before, ctx->_Shader could point to freed memory when _mesa_reference_pipeline_object(ctx, &ctx->_Shader, NULL) was called. Fixes crash when exiting the piglit rendezvous_by_location test on Windows. Cc: [email protected] Reviewed-by: Ian Romanick <[email protected]>
* ra: assert against unsigned underflow in q_totalConnor Abbott2014-09-121-0/+1
| | | | | | | | q_total should never go below 0 (which is why it's defined as unsigned), and if it does, then something is seriously wrong. Signed-off-by: Connor Abbott <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* ra: note a restriction in the interfence graph APIConnor Abbott2014-09-121-1/+4
| | | | | | | | | As noted in the previous commit, this was introduced in 567e2769b81863b6dffdac3826a6b729ce6ea37c ("ra: make the p, q test more efficient"), but I forgot to mention it. Signed-off-by: Connor Abbott <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* r300g: set register classes before interferencesConnor Abbott2014-09-121-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 567e2769b81863b6dffdac3826a6b729ce6ea37c ("ra: make the p, q test more efficient") I unknowingly introduced a new requirement to the register allocator API: the user must set the register class of all nodes before setting up their interferences, because ra_add_conflict_list() now uses the classes of the two interfering nodes. i965 already did this, but r300g was setting up register classes interleaved with setting up the interference graph. This led to us calculating the wrong q total, and in certain cases e78a01d5e6f77e075fe667a0f0ccb10d89c0dd58 (" ra: optimistically color only one node at a time") made it so that this bug caused a segfault. In particular, the error occurred if the q total was decremented to 1 below 0 for the last node to be pushed onto the stack. Since q_total is an unsigned integer, it overflowed to 0xffffffff, which is what lowest_q_total happens to be initialzed to. This means that we would fail the "new_q_total < lowest_q_total" check on line 476 of register_allocate.c, and so the node would never be pushed onto the stack, which led to segfaults in ra_select() when we failed to ever give it a register. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82828 Cc: "10.3" <[email protected]> Signed-off-by: Connor Abbott <[email protected]> Tested-by: Pavel Ondračka <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* gallium/util: add missing u_debug includeAndreas Boll2014-09-121-0/+1
| | | | | | | | | | | | | | | | | | | Needed for assert. Fixes build on BE archs with -Werror=implicit-function-declaration. In file included from ../../../../../src/gallium/auxiliary/draw/draw_fs.c:30:0: ../../../../../src/gallium/auxiliary/util/u_math.h: In function 'util_memcpy_cpu_to_le32': ../../../../../src/gallium/auxiliary/util/u_math.h:810:4: error: implicit declaration of function 'assert' [-Werror=implicit-function-declaration] assert(n % 4 == 0); ^ Cc: "10.3" <[email protected]> Signed-off-by: Andreas Boll <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ilo: fix builder size checks for BLT buffer clear/copyChia-I Wu2014-09-121-4/+8
| | | | | | | | | In buf_clear_region() and buf_copy_region(), max_cmd_size was set to 0. If either of the functions is called and there is not enough space in the builder, the next ilo_cp_flush() will fail silently in a release build. Replace magic numbers by size defines in tex_clear_region()/tex_copy_region() for consistency and readability.
* ilo: reduce BLT function parametersChia-I Wu2014-09-122-142/+171
| | | | | Intruduce gen6_blt_bo and gen6_blt_xy_bo to describe BOs. In the extreme case of gen6_XY_SRC_COPY_BLT(), the number of parameters goes down from 18 to 8.
* ilo: clean up BLT functionsChia-I Wu2014-09-122-104/+91
| | | | Follow the changes for MI functions, but for BLT this time.
* ilo: clean up MI functionsChia-I Wu2014-09-123-40/+45
| | | | | With ilo_builder in place, some conventions we had to build commands are no longer needed.
* ilo: move BLT functions to ilo_builder_blt.hChia-I Wu2014-09-123-257/+296
| | | | Follow the changes for MI functions, but for BLT this time.
* ilo: move MI functions to ilo_builder_mi.hChia-I Wu2014-09-128-168/+192
| | | | | Have a centralized place for MI functions, and remove the duplicated gen6_MI_LOAD_REGISTER_IMM().
* ilo: add ILO_DEV_ASSERT()Chia-I Wu2014-09-125-113/+118
| | | | It replaces ILO_GPE_VALID_GEN().
* ilo: use an accessor for dev->genChia-I Wu2014-09-1224-171/+198
| | | | | It should enable us to do specialized builds by making the accessor return a constant.
* ilo: add GEN_EXTRACT() and GEN_SHIFT32()Chia-I Wu2014-09-124-133/+142
| | | | They replace READ() and SET_FIELD() that we have been using.
* ilo: remove ILO_GEN_GET_MAJOR()Chia-I Wu2014-09-121-1/+0
| | | | The last user has gone away.
* ilo: careful with empty fb state in ilo_gpe_set_fb()Chia-I Wu2014-09-122-1/+6
| | | | We cannot pass 0 as the width or height to ilo_gpe_init_view_surface_null().
* nv50,nvc0: enable ARB_texture_viewIlia Mirkin2014-09-126-7/+69
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* mesa/st: add ARB_texture_view supportIlia Mirkin2014-09-126-18/+105
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: add a texture target to sampler view and a CAP to use itIlia Mirkin2014-09-1217-0/+20
| | | | | | | | | | This allows a sampler view to have a different texture target than the underlying resource. This will be used to implement the type casting between 2d arrays and cube maps as specified in ARB_texture_view. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nouveau: only enable stencil func if the visual has stencil bitsIlia Mirkin2014-09-122-2/+2
| | | | | | | The _Enabled property already has the relevant information. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.2 10.3" <[email protected]>
* nouveau: only enable the depth test if there actually is a depth bufferIlia Mirkin2014-09-125-4/+9
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.2 10.3" <[email protected]>
* nouveau: remove unneeded assertMaarten Lankhorst2014-09-111-1/+0
| | | | | | | | No idea why it was added, but the code runs fine even on videos where it triggers. Signed-off-by: Maarten Lankhorst <[email protected]> Cc: "10.2 10.3" <[email protected]>
* nouveau: rework reference frame handlingMaarten Lankhorst2014-09-113-4/+37
| | | | | | | | | | | | Fixes a regression from "nouveau/vdec: small fixes to h264 handling" New picking order for frames: 1. Vidbuf pointer matches. 2. Take the first kicked ref. 3. If that fails, take a ref that has a different last_used. Signed-off-by: Maarten Lankhorst <[email protected]> Cc: "10.2 10.3" <[email protected]>
* nouveau: fix MPEG4 hw decodingMaarten Lankhorst2014-09-111-3/+3
| | | | | | | Reorder some fields to make I-frame decoding work correctly. Signed-off-by: Maarten Lankhorst <[email protected]> Cc: "10.2 10.3" <[email protected]>
* nouveau: re-allocate bo's on overflowMaarten Lankhorst2014-09-114-11/+87
| | | | | | | | | The BSP bo might be too small to contain all of the bsp data, bump its size on overflow. Also bump inter_bo when this happens, it might be too small otherwise. Signed-off-by: Maarten Lankhorst <[email protected]> Cc: "10.2 10.3" <[email protected]>
* ilo: fix a compile error with -Werror=format-securityChia-I Wu2014-09-121-1/+1
| | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83777
* i965/vec4: Only examine virtual_grf_end for GRF sourcesIan Romanick2014-09-111-8/+12
| | | | | | | | | | | | | If the source is not a GRF, it could have a register >= virtual_grf_count. Accessing virtual_grf_end with such a register would lead to out-of-bounds access. Make sure the source is a GRF before accessing virtual_grf_end. Fixes Valgrind complaints while compiling some shaders. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* st/mesa: handle failed context creation for core profileBrian Paul2014-09-112-34/+53
| | | | | | | | | | | | If the glx/wgl state tracker requested a core profile but the gallium driver did not support some feature of GL 3.1 or later, we were setting ctx->Version=0 and then failing the assertion in _mesa_initialize_exec_table(). With this change we check for ctx->Version=0 and tear down the context and return NULL from st_create_context(). Reviewed-by: Marek Olšák <[email protected]>
* i965: Implement GL_PRIMITIVES_GENERATED with non-zero streams.Iago Toral Quiroga2014-09-111-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far we have been using CL_INVOCATION_COUNT to resolve this query but this is no good with streams, as only stream 0 reaches the clipping stage. From ARB_transform_feedback3: "When a generated primitive query for a vertex stream is active, the primitives-generated count is incremented every time a primitive emitted to that stream reaches the Discarding Rasterization stage (see Section 3.x) right before rasterization. This counter is incremented whether or not transform feedback is active." Unfortunately, we don't have any registers that provide the number of primitives written to a specific stream other than the ones that track the number of primitives written to transform feedback in the SOL stage, so we can't implement this exactly as specified. In the past we implemented this feature by activating the SOL unit even if transform feeback was disabled, but making it so that all buffers were disabled and it only recorded statistics, which gave us the right semantics (see 3178d2474ae5bdd1102fb3d76a60d1d63c961ff5). Unfortunately, this came with a significant performance impact and had to be reverted. This new take does not intend to implement the exact semantics required by the spec, but improves what we have now, since now we return the primitive count for stream 0 in all cases. With this patch we use GEN7_SO_PRIM_STORAGE_NEEDED to resolve GL_PRIMITIVES_GENERATED queries for non-zero streams. This would return the number of primitives written to transform feedback for each stream instead. Since non-zero streams are only useful in combination with transform feedback this should not be too bad, and the only case that I think we would not be supporting would be the one in which we want to use both GL_PRIMITIVES_GENERATED and GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN on the same non-zero stream to detect buffer overflow. This patch also fixes the following piglit test: arb_gpu_shader5-xfb-streams-without-invocations This test uses both GL_PRIMITIVES_GENERATED and GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN queries on non-zero streams, but it does never hit the overflow case, so both queries are always expected to return the same value. Reviewed-by: Kenneth Graunke <[email protected]> Cc: "10.3" <[email protected]>
* radeon/uvd: use PIPE_USAGE_STAGING for msg&fb buffersChristian König2014-09-111-1/+1
| | | | | | | | That better matches the actual userspace use case, the kernel will force it to VRAM if the hardware requires it. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeon/video: use the hw to initial clear the buffersChristian König2014-09-113-10/+8
| | | | | | | Less CPU overhead and avoids contention over CPU accessible memory on startup. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeon/video: use more of the common buffer code v2Christian König2014-09-116-67/+62
| | | | | | | | | In preparation to using buffers clears with the hw engine(s). v2: split out flipping to using hw buffer clears. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* scons: add /dynamicbase and /nxcompat to MinGW linkflagsJosé Fonseca2014-09-111-2/+6
| | | | Just like b26503b196d51dc46c815e241343e42ab30e8d66 for MSVC.
* scons: add /dynamicbase and /nxcompat to MSVC linkflagsBrian Paul2014-09-111-0/+2
| | | | | | | This builds the opengl DLLs with address layout space randomization (ASLR) and data execution prevention (DEP) for better security. Reviewed-by: Kurt Daverman <[email protected]>
* ilo: add a new disassemblerChia-I Wu2014-09-113-4444/+1352
| | | | | | | | The old disassembler was modified from i965's. It is as much work as doing a new one to keep it up-to-date, which also requires copying more headers over. The outputs of this new disassembler should match i965's as closely as possible.
* ilo: update genhw headersChia-I Wu2014-09-1111-247/+203
| | | | | | | | Add some new registers and some tweaks. The changes that affect ilo are GEN6_REG_HS_INVOCATION_COUNT -> GEN7_REG_HS_INVOCATION_COUNT GEN6_REG_DS_INVOCATION_COUNT -> GEN7_REG_DS_INVOCATION_COUNT GEN6_COND_NORMAL -> GEN6_COND_NONE
* glsl: allow precision qualifier on sampler arraysFrank Henigman2014-09-111-34/+41
| | | | | | | | | | | If a precision qualifer is allowed on type T, it should be allowed on an array of T. Refactor the check to ensure this is the case. (Fixes failures in WebGL conformance test 'gl-min-textures') Signed-off-by: Frank Henigman <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
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