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* st/mesa: make user index buffers optionalMarek Olšák2012-04-303-1/+16
| | | | v2: use a separate upload buffer for indices
* st/mesa: only set index buffer when drawing is indexedMarek Olšák2012-04-301-25/+21
| | | | and restructure the code a bit
* gallium: add PIPE_CAP_USER_INDEX_BUFFERS and PIPE_CAP_USER_CONSTANT_BUFFERSMarek Olšák2012-04-3012-0/+28
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* scons: Parse = operator in source lists too.José Fonseca2012-04-291-5/+6
| | | | Should fix the scons build.
* nv50,nvc0: fix depth/stencil resolveChristoph Bumiller2012-04-295-56/+206
| | | | | Cannot sample depth/stencil with a single view, and needed to use different shader code for nve4.
* nvc0/ir/opt: INTERP does not support JOINChristoph Bumiller2012-04-291-0/+2
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* nv50/ir/opt: try to convert ABS(SUB) to SADChristoph Bumiller2012-04-297-16/+179
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* nvc0/ir: try to use the optimal texture op modeChristoph Bumiller2012-04-291-3/+15
| | | | | Don't really know what they are yet but for groups of textures, the last one should use mode "p" and the others "t".
* nvc0/ir: initial implementation of nve4 scheduling hintsChristoph Bumiller2012-04-298-15/+738
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* nvc0/ir: implement better placement of texture barriersChristoph Bumiller2012-04-298-13/+327
| | | | | Put them before first uses instead of right after the texturing instruction and cull unnecessary barriers.
* nv50/ir/tgsi: fix handling of early RETChristoph Bumiller2012-04-291-4/+5
| | | | We have to actually emit RET, too, of course, not just the PRERET.
* nvc0/ir/emit: fix emitTXQ 2nd srcChristoph Bumiller2012-04-291-1/+3
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* nvc0/ir/target: integer ADD doesn't support ABS modifierChristoph Bumiller2012-04-291-0/+2
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* u_vbuf: unbind vertex buffers on destroyMarek Olšák2012-04-291-0/+2
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* u_blitter: fix resource leakMarek Olšák2012-04-291-0/+1
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* radeonsi: make r600_buffer_transfer_unmap a no-opMarek Olšák2012-04-291-7/+1
| | | | It's a no-op already in the winsys.
* r600g: make r600_buffer_transfer_unmap a no-opMarek Olšák2012-04-291-7/+1
| | | | It's a no-op already in the winsys.
* r300g: make r300_buffer_transfer_unmap a no-opMarek Olšák2012-04-291-7/+1
| | | | It's a no-op already in the winsys.
* r300g: use u_default_transfer_inline_writeMarek Olšák2012-04-293-31/+3
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* radeonsi: use u_default_transfer_inline_writeMarek Olšák2012-04-293-26/+3
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* winsys/radeon: simplify buffer map/unmap functionsMarek Olšák2012-04-2921-118/+94
| | | | | The idea is not to use pb_map and pb_unmap wrappers, calling straight into the winsys.
* mesa: require GL_MAX_SAMPLES >= 4 for GL 3.0Dylan Noblesmith2012-04-291-0/+1
| | | | | | | | | As noted in commit be4e46b21a60cfdc826bf89d1078df54966115b1, this was missing before. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Kenneth Graunke <[email protected]>
* autoconf: pass -Wall to automakeDylan Noblesmith2012-04-295-10/+10
| | | | | | | And fix these warning that appear at autoreconf time: "`:='-style assignments are not portable" v2: Fix the recently-converted-to-automake r600.
* glsl: Remove unused member predicate from ir_dead_functions_visitor.Vinson Lee2012-04-281-2/+0
| | | | | | | Fix uninitialized pointer field defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Fix FB writes that tried to use the non-existent m16 register.Kenneth Graunke2012-04-271-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A little analysis shows that the worst-case value for "nr" is 17: - base_mrf = 2 ... 2 - header present (say gen == 5) ... 4 - aa_dest_stencil_reg (stencil test) ... 5 - SIMD16 mode: += 4 * reg_width ... 13 - source_depth_to_render_target ... 15 - dest_depth_reg ... 17 This resulted in us setting base_mrf to 2 and mlen to 15. In other words, we'd try to use m2..m16. But m16 doesn't exist pre-Gen6. Also, the instruction scheduler data structures use arrays of size 16, so this would cause us to access them out of bounds. While the debugger system routine may need m0 and m1, we don't use it today, so the simplest solution is just to move base_mrf back to 1. That way, our worst case message fits in m1..m15, which is legal. An alternative would be to fail on SIMD16 in this case, but that seems a bit unfortunate if there's no real need to reserve m0 and m1. Fixes new piglit test shaders/depth-test-and-write on Ironlake. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48218 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: Remove unused member mem_ctx from ir_dead_functions_visitor.Vinson Lee2012-04-261-1/+0
| | | | | | | Fix uninitialized pointer field defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nv30: properly init window informationBen Skeggs2012-04-272-3/+4
| | | | | | Should fix >2k rendering issues reported on nv4x. Signed-off-by: Ben Skeggs <[email protected]>
* radeonsi/llvm: Silence a warningTom Stellard2012-04-251-0/+1
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* radeon/llvm: Remove unused header filesTom Stellard2012-04-252-115/+0
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* radeon/llvm: Remove AMDILMachineFunctionInfo.cppTom Stellard2012-04-2514-1176/+6
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* radeon/llvm: Remove AMDILModuleInfo.cppTom Stellard2012-04-254-1432/+0
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* gallivm: Use lp_build_alloca instead of LLVMBuildAlloca on the loop limiter.José Fonseca2012-04-251-4/+1
| | | | | | | To ensure that the alloca is at the top of the function body, otherwise LLVM will not eliminate them, causing stack misalignment on 32bits. Reviewed-by: James Benton <[email protected]>
* radeon/llvm: Remove AMDILELFWriterInfo.cppTom Stellard2012-04-255-137/+1
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* radeon/llvm: Remove AMDILLiteralManager.cppTom Stellard2012-04-254-129/+0
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* radeon/llvm: Remove AMDILInliner.cppTom Stellard2012-04-255-276/+0
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* radeon/llvm: Remove AMDILBarrierDetect.cppTom Stellard2012-04-255-259/+0
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* radeon/llvm: Remove AMDILPrintfConvert.cppTom Stellard2012-04-255-295/+0
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* radeon/llvm: Remove GlobalManager and KernelManagerTom Stellard2012-04-2511-3275/+23
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* radeon/llvm: Remove AsmPrinter filesTom Stellard2012-04-255-443/+0
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* radeon/llvm: Remove IOExpansion filesTom Stellard2012-04-2515-4048/+0
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* radeon/llvm: Remove AMDILPointerManager.cppTom Stellard2012-04-2510-2789/+0
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* radeonsi/llvm: Fix initialization of SIMachineFunctionInfoTom Stellard2012-04-251-4/+4
| | | | | SIMachineFunctionInfo needs to be initialized before any of the AMDIL passes.
* mesa/st: Fix derreference after free.José Fonseca2012-04-251-2/+6
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* gallium/docs: document the new vertex fetch CAPsMarek Olšák2012-04-241-0/+12
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* nv50: fix typo in nv50_fragprog_assign_slotsChristoph Bumiller2012-04-241-1/+1
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* glsl: Add implementation of inverse() for mat2/3/4.Eric Anholt2012-04-243-1/+111
| | | | | | | | | | | | This is taken from the ogl-math project, with Inverse renamed to adj (since it's not actually the inverse), transposed, and our types plugged in. There are potential CSE opportunities in this code (particularly for hardware with RCP but not DIV), but we should be doing CSE anyway, so don't hand-optimize. Fixes piglit inverse tests. Acked-by: Kenneth Graunke <[email protected]>
* glsl: Add support for generating builtin code from GLSL instead of IR.Eric Anholt2012-04-241-4/+16
| | | | | | | | This takes advantage of the builtin compiler to generate IR into a string, the same way we read GLSL for function prototypes for our profiles. Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Make ir_reader parse the "temporary" variable qualifier.Eric Anholt2012-04-241-0/+2
| | | | | | | This lets ir_reader eat the output of builtin_compiler on actual function definitions. Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Add doxygen explaining what main.cpp is for.Eric Anholt2012-04-241-0/+9
| | | | | | | I keep getting lost in the Makefile trying to figure out what to edit to work on builtin_compiler or glsl_compiler. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Fix texelFetchOffset()Eric Anholt2012-04-241-3/+23
| | | | | | It appears that when using 'ld' with the offset bits, address bounds checking happens before the offset is applied, so parts of the drawing in piglit texelFetchOffset() with a negative texcoord go black.
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