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* i965/vec4: slightly improve insn dumping with no srcsChris Forbes2014-09-171-1/+4
| | | | | | | Previously, we would get a trailing ', ' which looked strange. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* vc4: Add support for computed depth writes.Eric Anholt2014-09-163-2/+26
| | | | Fixes piglit glsl-1.10-fragdepth and early-z.
* vc4: Restructure depth input/output in fragment shaders.Eric Anholt2014-09-164-12/+17
| | | | | | The goal here is to have an argument for the depth write opcode so that I can do computed depth. In the process, this makes the calculations that will be emitted more obvious in the QIR.
* freedreno: add a standalone ir3_compiler binary for building TGSIIlia Mirkin2014-09-162-0/+191
| | | | | | Compiler taken from the combo old/new compiler comparer + simulator. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno: add default .dir-locals.el for emacs settingsIlia Mirkin2014-09-161-0/+8
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* i965: add support for RGBA dma_buf imports.Gwenole Beauchesne2014-09-161-0/+6
| | | | | | | | | This allows for importing foreign buffers in RGB32 native endian byte order, i.e. DRM_FORMAT_XBGR8888, and DRM_FORMAT_ABGR8888. Signed-off-by: Gwenole Beauchesne <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Cc: "10.3" <[email protected]>
* i965: Mark delta_x/y as BAD_FILE if remapped away completely.Kenneth Graunke2014-09-162-5/+15
| | | | | | | | | | | | | | | | | | | | | | | Commit afe3d1556f6b77031f7025309511a0eea2a3e8df (i965: Stop doing remapping of "special" regs.) stopped remapping delta_x/delta_y, and additionally stopped considering them always-live. We later realized delta_x was used in register allocaiton, so we actually needed to remap it, which was fixed in commit 23d782067ae834ad53522b46638ea21c62e94ca3 (i965/fs: Keep track of the register that hold delta_x/delta_y.). However, that commit didn't restore the "always consider it live" part. If all the code using delta_x was eliminated, fs_visitor::delta_x would be left pointing at its old register number. Later code in register allocation would handle that register number specially...even though it wasn't actually delta_x. To combat this, set delta_x/y to BAD_FILE if they're eliminated, and check for that. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83127 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Cc: "10.3" <[email protected]>
* st_glsl_to_tgsi: init have_sqrt field.Dave Airlie2014-09-161-0/+1
| | | | | | Coverity reported this. Signed-off-by: Dave Airlie <[email protected]>
* llvmpipe: fix rast debugging outputDave Airlie2014-09-161-0/+11
| | | | | | | | The triangle_32_ rast functions never made it into the debug output, confused me for a few seconds. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* util: Add big-endian layout for a number of formats.Richard Sandiford2014-09-162-35/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch builds on 6c8f547f66e68b495c708f8ffcb67370caa5ffe8 and previous patches by allowing u_format.csv to specify separate big-endian and little-endian layouts. It then uses this to specify the correct layouts for various depth/stencil formats. Later patches handle other formats. To recap, the idea is that u_format.csv lists the channels for an N-byte value as though it were an N-byte integer. For little-endian targets the channels are listed starting at the least-significant bit of the integer while for big-endian targets the channels are listed starting at the most-significant bit. This means that for something like PIPE_FORMAT_B8G8R8A8_UNORM (blue in first byte of memory, alpha in last byte of memory) the orders are the same for both endiannesses. But for something like PIPE_FORMAT_S8_UINT_Z24_UNORM, where the stencil is in the least significant byte of a 32-bit integer, there need to be separate channel definitions for each endianness. The effect of this patch is to make the affected PIPE_FORMAT_*s have the same layout as the associated MESA_FORMAT_*s for big-endian. The MESA_FORMAT_*s are already handled correctly. Fixes various piglit tests on z. No regressions on x86_64. [airlied: squash subsequent patches] util: Add big-endian layout for 5551 and 565 formats util: Add big-endian layout for 10/10/10/2 formats util: Add big-endian layout for 4444 formats util: Add big-endian layout for 233 format util: Add big-endian layout for 44 formats Signed-off-by: Dave Airlie <[email protected]>
* llvmpipe: Fix PIPE_FORMAT_Z32_FLOAT_S8X24_UINT handling for big-endian.Richard Sandiford2014-09-161-1/+2
| | | | | | | | | | | | | | | | | llvmpipe treats PIPE_FORMAT_Z32_FLOAT_S8X24_UINT as a bit of a special case, handling it as two 32-bit pieces rather than a single 64-bit block: /* 64bit d/s format is special already extracted 32 bits */ total_bits = format_desc->block.bits > 32 ? 32 : format_desc->block.bits; The format_desc describes the whole 64-bit block, so the z shift will be 32 for big-endian. But since we're accessing the z channel as a 32-bit value rather than a 64-bit value, we need to mask the shift with 31. Signed-off-by: Richard Sandiford <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallivm: Fix uses of 2^24Richard Sandiford2014-09-161-4/+4
| | | | | | | | | | Fallback cases in lp_bld_arit.c used 2^24 to mean "2 to the power 24", but in C it's "2 xor 24", i.e. 26. Fixed by using 1<< instead. Signed-off-by: Richard Sandiford <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Cc: "10.2 10.3" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallivm: Add SNORM clamping to lp_build_{add, sub}Richard Sandiford2014-09-161-6/+28
| | | | | | | ...fixing the associated TODO. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Richard Sandiford <[email protected]>
* gallivm: attach DataLayout to module too, not just pass manager.Rafael Ávila de Espíndola2014-09-161-0/+7
| | | | | | | | | It looks like it was possible to attach it to both for a long time, however since llvm r217548 attaching it to just the pass manager is no longer sufficient and causes bugs (see http://llvm.org/bugs/show_bug.cgi?id=20903). Tested-by: Vinson Lee <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: handle SAMPLE opcode in aos samplingRoland Scheidegger2014-09-162-13/+50
| | | | | | | | | | | This is just a very limited version, in particular sampler and sampler view index must be the same. It cannot handle any modifiers neither. Works much the same as soa version otherwise, to figure out the target we need to store the sampler view dcls. While here, also handle (no-op) RET and get rid of a couple bogus deprecated comments. Reviewed-by: Jose Fonseca <[email protected]>
* tgsi: accept offsets for sample opcodes too in the text parserRoland Scheidegger2014-09-161-3/+2
| | | | | | | | | | sample opcodes are a little oddly represented in the opcode_info, since they don't count as texture instructions - they don't have valid target information, but they may have offsets (unlike "ordinary" texture instructions, the texture token may be optional for them). So just make sure with these opcodes the optional offsets are accepted. Reviewed-by: Jose Fonseca <[email protected]>
* tgsi: don't print texture target for sample opcodesRoland Scheidegger2014-09-161-2/+5
| | | | | | | | sample opcodes don't encode a texture target, it would thus always print UNKNOWN, which is not helpful (and wouldn't parse when giving back the shader text to tgsi). Reviewed-by: Jose Fonseca <[email protected]>
* vc4: Bump maximum ARB program temporaries to match Intel/AMD.Eric Anholt2014-09-151-1/+1
| | | | | This query has always been useless, but we could potentially reject well-formed, runnable programs if we expose a value that's too low.
* vc4: Bump maximum uniforms count to match other drivers.Eric Anholt2014-09-151-1/+1
| | | | | | We don't have any specific limits in the hardware, just like the other GPUs, so match their behavior. Fixes minmax_gles2 and several other piglit tests relying on the specced uniform minmax values.
* vc4: Dynamically allocate the TGSI-to-qreg arrays.Eric Anholt2014-09-152-12/+44
| | | | | Fixes buffer overflows in some piglit tests (which are still failing to register allocate anyway).
* vc4: Fix memory leaks of struct qinst.Eric Anholt2014-09-154-3/+17
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* vc4: Fix memory leaks of some vc4_compile contents.Eric Anholt2014-09-152-10/+11
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* vc4: Reuse the util header instead of defining our own ARRAY_SIZE.Eric Anholt2014-09-151-2/+1
| | | | | Fixes redefinition warnings if you end up including this header before util stuff.
* mesa: move i, j var decls into SWIZZLE_CONVERT_LOOP() macroBrian Paul2014-09-151-36/+38
| | | | | | | Put macro code in do {} while loop and put semicolons on macro calls so auto indentation works properly. Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: break up _mesa_swizzle_and_convert() to reduce compile timeBrian Paul2014-09-151-480/+550
| | | | | | | This reduces gcc -O3 compile time to 1/4 of what it was on my system. Reduces MSVC release build time too. Reviewed-by: Jason Ekstrand <[email protected]>
* Generate a warning when not writing gl_Position with GLES.Kalyan Kondapally2014-09-151-2/+9
| | | | | | | | | | With GLES we don't give any kind of warning in case we don't write to gl_position. This patch makes changes so that we generate a warning in case of GLES (VER < 300) and an error in case of GL. Signed-off-by: Kalyan Kondapally <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* mesa: check that uniform exists in glUniform* functionsTapani Pälli2014-09-151-8/+8
| | | | | | | | | | | | | Remap table for uniforms may contain empty entries when using explicit uniform locations. If no active/inactive variable exists with given location, remap table contains NULL. v2: move remap table bounds check before existence check (Ian Romanick) Signed-off-by: Tapani Pälli <[email protected]> Tested-by: Erik Faye-Lund <[email protected]> (v1) Reviewed-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83574
* ilo: clean up 3D/media functionsChia-I Wu2014-09-153-205/+188
| | | | Mostly style changes to set dw[0] directly.
* ilo: fix gen6_3DSTATE_MULTISAMPLE()Chia-I Wu2014-09-151-1/+1
| | | | There was a typo introduced by 90f4b131fccae3a950864ed9ba15eea8edce915f.
* freedreno/a3xx: 3d/array texturesRob Clark2014-09-134-7/+102
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-09-134-4/+22
| | | | Signed-off-by: Rob Clark <[email protected]>
* ilo: trust vertex element count moreChia-I Wu2014-09-141-3/+2
| | | | | | | | | | | We might run into ve->count == 0 and last_velement_edgeflag == true in gen6_3DSTATE_VERTEX_ELEMENTS() when the state tracker sets an invalid combination of VS and VE (does not seem to happen with st/mesa). Do not assume ve->count is positive when last_velement_edgeflag is true. Reported by Coverity. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: simplify src operand gathering in disassemblerChia-I Wu2014-09-141-15/+5
| | | | | | Always initialize the operand array to point to src0, src1, and src2. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: derive 3-src instructions from the opcode tableChia-I Wu2014-09-141-9/+2
| | | | | | One less switch statement to maintain. Signed-off-by: Chia-I Wu <[email protected]>
* nouveau: check for mesa context init failureIlia Mirkin2014-09-131-2/+2
| | | | | | Reported by Coverity Signed-off-by: Ilia Mirkin <[email protected]>
* nouveau: avoid leaking screen on initialization failIlia Mirkin2014-09-131-2/+5
| | | | | | Reported by Coverity Signed-off-by: Ilia Mirkin <[email protected]>
* nouveau: change internal variables to avoid conflicts with macro argsIlia Mirkin2014-09-131-10/+10
| | | | | | | Reported by Coverity Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.2 10.3" <[email protected]>
* ilo: clean up 3DPRIMITIVE functionsChia-I Wu2014-09-135-25/+24
| | | | Add ILO_PRIM_RECTANGLES to replace the rectlist bool.
* ilo: clean up 3D/media common functionsChia-I Wu2014-09-133-120/+42
| | | | | | Rename ilo_builder_batch_state_base_address() to gen6_state_base_address() for consistency and remove unused gen6_STATE_BASE_ADDRESS(). Reorder the code in gen6_PIPE_CONTROL() a bit. Finally, some mostly cosmetic changes.
* ilo: move 3D functions to ilo_builder_3d*.hChia-I Wu2014-09-139-2538/+2614
| | | | | | Move functions for the 3D pipeline to the new headers. We artificially split the functions into top (vertex processing) and bottom (pixel processing), to keep the headers at reasonable sizes.
* ilo: move media functions to ilo_builder_media.hChia-I Wu2014-09-134-173/+211
| | | | Move functions for the media pipeline to the new header.
* ilo: move GPE common functions to ilo_builder_render.hChia-I Wu2014-09-137-267/+303
| | | | Move 3D/media common functions to the new header.
* glsl: Speed up constant folding for swizzles.Kenneth Graunke2014-09-121-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ir_rvalue::constant_expression_value() recursively walks down an IR tree, attempting to reduce it to a single constant value. This is useful when you want to know whether a variable has a constant expression value at all, and if so, what it is. The constant folding optimization pass attempts to replace rvalues with their constant expression value from the bottom up. That way, we can optimize subexpressions, and ideally stop as soon as we find a non-constant subexpression. In order to obtain the actual value of an expression, the optimization pass calls constant_expression_value(). But it should only do so if it knows the value can be combined into a constant. Otherwise, at each step of walking back up the tree, it will walk down the tree again, only to discover what it already knew: it isn't constant. We properly avoided this call for ir_expression nodes, but not for ir_swizzle nodes. This patch fixes that, drastically reducing compile times on certain shaders where tree grafting has given us huge expression trees. It also fixes SuperTuxKart. Thanks to Iago and Mike for help in tracking this down. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78468 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Cc: [email protected]
* i965/vec4: Make type_size() return 0 for samplers.Kenneth Graunke2014-09-121-3/+3
| | | | | | | | | | | | | | The FS backend has always used 0, and the VS backend has always used 1. I think 1 is just working around other problems, and is incorrect. Samplers are baked in; nothing uses the UNIFORM register we would create, and we shouldn't upload any constant values for them. Fixes ES3-CTS.shaders.struct.uniform.sampler_array_vertex. Signed-off-by: Kenneth Graunke <[email protected]> Cc: [email protected] Reviewed-by: Ian Romanick <[email protected]> Tested-by: Ian Romanick <[email protected]>
* i965: Skip allocating UNIFORM file storage for uniforms of size 0.Kenneth Graunke2014-09-122-6/+6
| | | | | | | | | | | | | | | | | | | | | Samplers take up zero slots and therefore don't exist in the params array, nor are they included in stage_prog_data->nr_params. There's no need to store their size in param_size, as it's only used for dealing with arrays of "real" uniforms (ones uploaded as shader constants). We run into all kinds of problems trying to refer to the uniform storage for variables that don't have uniform storage. For one, we may use some other variable's index, or access out of bounds in arrays. In the FS backend, our extra 2 * MaxSamplerImageUnits params for texture rectangle rescaling paper over a lot of problems. In the VS backend, we claim samplers take up a slot, which also papers over problems. Instead, just skip allocating storage for variables that don't have any. Signed-off-by: Kenneth Graunke <[email protected]> Cc: [email protected] Reviewed-by: Ian Romanick <[email protected]> Tested-by: Ian Romanick <[email protected]>
* i965: Separate gl_InstanceID and gl_VertexID uploading.Kenneth Graunke2014-09-125-16/+42
| | | | | | | | | | | | | | | | We always uploaded them together, mostly out of laziness - both required an additional vertex element. However, gl_VertexID now also requires an additional vertex buffer for storing gl_BaseVertex; for non-indirect draws this also means uploading (a small amount of) data. This is extra overhead we don't need if the shader only uses gl_InstanceID. In particular, our clear shaders currently use gl_InstanceID for doing layered clears, but don't need gl_VertexID. Signed-off-by: Kenneth Graunke <[email protected]> Cc: "10.3" <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Ian Romanick <[email protected]>
* i965: Fix reference counting in new basevertex upload code.Kenneth Graunke2014-09-121-0/+3
| | | | | | | | | | | | | | | | | | | | In the non-indirect draw case, we call intel_upload_data to upload gl_BaseVertex. It makes brw->draw.draw_params_bo point to the upload buffer, and increments the upload BO reference count. So, we need to unreference it when making brw->draw.draw_params_bo point at something else, or else we'll retain a reference to stale upload buffers and hold on to them forever. This also means that the indirect case should increment the reference count on the indirect draw buffer when making brw->draw.draw_params_bo point at it. That way, both paths increment the reference count, so we can safely unreference it every time. Signed-off-by: Kenneth Graunke <[email protected]> Cc: "10.3" <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Ian Romanick <[email protected]>
* freedreno: "fix" problems with excessive flushesRob Clark2014-09-125-27/+14
| | | | | | | | | | | | | | | | | | | | | | | 4f338c9b introduced logic to trigger a flush rather than overflowing cmdstream buffer. But the threshold was too low, triggering flushes where they were not needed. This caused problems with games like xonotic. Part of the problem is that we need to mark all state dirty between cmdstream submit ioctls, because we cannot rely on state being preserved across ioctls. But even with that, there are still some problems that are still being debugged. For now: 1) correctly mark all state dirty 2) introduce FD_MESA_DEBUG flush flag to force rendering to be flushed between each draw, to trigger problems (so that I can debug) 3) use a more reasonable threshold so for normal usecases we don't trigger the problems This at least corrects the regression, but there is still more debugging to do. Signed-off-by: Rob Clark <[email protected]>
* r600g,radeonsi: add debug option which forces DMA for copy_region and blitMarek Olšák2014-09-1211-21/+52
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* freedreno/ir3: implement UMUL correctlyIlia Mirkin2014-09-121-1/+48
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
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