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* nouveau: make sure there's always room to emit a fenceIlia Mirkin2015-10-074-2/+8
| | | | | | | | | | | | I started seeing a lot of situations on nv30 where fence emission wouldn't fit into the previous buffer (causing assertions). This ensures that whenever checking for space, we always leave a bit of extra room for the fence emission commands. Adjusts the nv30 and nvc0 fence emission logic to bypass the space checking as well. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected] Reviewed-by: Samuel Pitoiset <[email protected]>
* vc4: use nir two-sided-color loweringBoyan Ding2015-10-062-24/+2
| | | | | | | | Similar to 9ffc1049ca (freedreno/ir3: use nir two-sided-color lowering). No piglit regression. Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* vc4: Fix a leak of the last color read/write surface on context destroy.Eric Anholt2015-10-061-0/+3
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* vc4: Fix a memory leak in the simulator case.Eric Anholt2015-10-061-1/+6
| | | | We validate per draw call, and need to free the shader per draw call, too.
* mesa: remove unneeded #include of colormac.hMark Janes2015-10-061-1/+0
| | | | Reviewed-by: Matt Turner <[email protected]>
* radeon/r200: remove unneeded #include of colormac.hMark Janes2015-10-0611-11/+0
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: remove unneeded #include of colormac.hMark Janes2015-10-062-2/+0
| | | | Reviewed-by: Matt Turner <[email protected]>
* i915: remove unneeded #include of colormac.hMark Janes2015-10-062-2/+0
| | | | Reviewed-by: Matt Turner <[email protected]>
* i915: Drop broken front_buffer_reading/drawing optimizationVille Syrjälä2015-10-063-41/+15
| | | | | | | | | | | | | | | | | | | | | Bring the following commit over to i915: commit ec542d74578bbef6b55125dd6aba1dc7f5079e65 Author: Eric Anholt <[email protected]> Date: Mon Mar 3 10:43:10 2014 -0800 i965: Drop broken front_buffer_reading/drawing optimization. Not sure if it might fix anything, but since the i965 and i915 used to share a bunch of that code, it would seem reasonable the same problems could be present in the i915 code still, and the i965 approach is well tested by now so bringing it over seems fairly safe. No piglit regressions on 855. v2: Rebase on _mesa_is_front_buffer_* refactor. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa/i965: Refactor brw_is_front_buffer_{drawing,reading} to common codeIan Romanick2015-10-066-33/+37
| | | | | | | | | | There are multiple similar implementations of these functions, and a later patch was going to add another. v2: Move removing intel_framebuffer to a different patch. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* st/mesa: Don't override NewFramebuffer just to call _mesa_new_framebufferIan Romanick2015-10-061-12/+1
| | | | | | | | | v2: Since state_tracker does not call _mesa_init_driver_functions, we need to initialize the dd::NewFramebuffer pointer to _mesa_new_framebuffer here. Suggested by Brian. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeon: Don't override NewFramebuffer just to call _mesa_new_framebufferIan Romanick2015-10-061-7/+0
| | | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* i915: Don't override NewFramebuffer just to call _mesa_new_framebufferIan Romanick2015-10-062-15/+0
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: Don't override NewFramebuffer just to call _mesa_new_framebufferIan Romanick2015-10-062-16/+0
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i830: Fix culling with user fbos on gen2Ville Syrjälä2015-10-061-0/+2
| | | | | | | | | | | | Flip the cull bits when rendering to a user fbo on gen2. This was already done on gen3 (since before git history starts) but was missing from the gen2 code. Fixes rendering of the driver+kart model in supertuxkart kart selection screen. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i915: Adjust line size limitsVille Syrjälä2015-10-061-2/+2
| | | | | | | | | | | | The hardware can draw lines 0.5 to 7.5 pixels wide. Adjust the limits to 1.0-7.0. The old limits seems to be from the era when i915 and i965 were sharing this code. Not really sure if 1.0-7.0 is correct. Maybe it could be 0.5.7.5 as those are the hw limits, or maybe some combination of the two? Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i915: Enable intel_render path for pointsVille Syrjälä2015-10-061-5/+3
| | | | | | | | | | | | | | | | | | The sub-pixel adjustment for points was killed off in commit 60d762aa625095a8c1f9597d8530bb5a6fa61b4c Author: Xiang, Haihao <[email protected]> Date: Wed Jan 2 11:38:51 2008 +0800 i915: Needn't adjust pixel centers. fix #12944 so if we don't need it in intel_tris.c we don't need it in intel_render.c either, which means we can allow intel_render.c to render points. No apparent regressions on PNV in ES1 or ES2 conformance. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i915: Use COPY_DWORDS for pointsVille Syrjälä2015-10-061-5/+1
| | | | | | | | | | | | | | The sub-pixel adjustment for points was killed off in commit 60d762aa625095a8c1f9597d8530bb5a6fa61b4c Author: Xiang, Haihao <[email protected]> Date: Wed Jan 2 11:38:51 2008 +0800 i915: Needn't adjust pixel centers. fix #12944 so we can just as well use COPY_DWORDS(). Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i915: Use _tnl_RenderClippedPolygon and _tnl_RenderClippedLineVille Syrjälä2015-10-061-17/+2
| | | | | | | | _tnl_RenderClippedPolygon and _tnl_RenderClippedLine already do most of what we want so use them. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i915: Handle provoking vertex in intelFastRenderClippedPoly()Ville Syrjälä2015-10-061-4/+12
| | | | | | | | | | | | | | intelFastRenderClippedPoly() renders the polygon using triangles. For polygons the provoking vertex is always the first one, and currently this function assumes that the provoking vertex for triangles is the last one. In case the user changed the provoking vertex convention, the hardware may be configured to treat the first vertex of triangles as the provoking vertex. So check the convention and emit the triangles in the appropriate order to avoid having to change the hardware provoking vertex convention for rendering polygons. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* t_dd_dmatmp: Check provoking vertex convention when rendering quadsVille Syrjälä2015-10-061-20/+26
| | | | | | | | | | When drawing quads using triangles we need to be careful to make the provoking vertices match when flat shading. v2: Major rebase on top of Ian's other t_dd_dmatmp.h work. Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Ian Romanick <[email protected]>
* t_dd_dmatmp: Disallow flat shading when rendering quad strips via tri stripsVille Syrjälä2015-10-061-5/+2
| | | | | | | | | | When rendering quad strips via tri strips we can't get the provoking vertex right, so disallow flat shading. v2: Major rebase on top of Ian's other t_dd_dmatmp.h work. Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Ian Romanick <[email protected]>
* t_dd_dmatmp: Allow flat shaded polygons with tri fansVille Syrjälä2015-10-061-2/+4
| | | | | | | | | | We can allow rendering flat shaded polygons using tri fans if we check the provoking vertex convention. v2 (idr): Remove _EXT suffixes from GL_FIRST_VERTEX_CONVENTION. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* t_dd_dmatmp: Replace fprintf with unreachableIan Romanick2015-10-061-12/+9
| | | | | | | | | | | | | | | | | | | | From http://lists.freedesktop.org/archives/mesa-dev/2015-May/084883.html: "There are no real error cases here, just dead code. validate_render() is supposed to make sure we never call these functions if the code can't actually render the primitives. The fprintf()+return branches should really just contain assert(0) or equivalent." I also rearranged the if-else-block in render_quad_strip_verts to look more like the other functions. A future patch is going to change a bunch of that code anyway. v2: Make "unreachable" message more descriptive. Suggested by Iago. Signed-off-by: Ian Romanick <[email protected]> Suggested-by: Ville Syrjälä <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* radeon: Use C99 initializers for primitive arraysIan Romanick2015-10-061-20/+20
| | | | | | | | | | Using C99 initializers for the primitive arrays makes things more readable. Signed-off-by: Ian Romanick <[email protected]> Suggested-by: Matt Turner <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Use C99 initializers for primitive arraysIan Romanick2015-10-061-24/+24
| | | | | | | | | Using C99 initializers for the primitive arrays makes things more readable. Signed-off-by: Ian Romanick <[email protected]> Suggested-by: Matt Turner <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i915: Use C99 initializers for primitive arraysVille Syrjälä2015-10-062-50/+50
| | | | | | | | | Using C99 initializers for the primitive arrays makes things more readable. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* tgsi: add const qualifier to silence warningBrian Paul2015-10-061-1/+1
| | | | Trivial.
* glsl: whitespace/formatting/typo fixes in link_uniforms.cppBrian Paul2015-10-061-6/+9
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* main: array stride for unsized arrays of arrays are calculated like recordsSamuel Iglesias Gonsalvez2015-10-061-1/+1
| | | | | Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* glsl: add std430 layout support for AoASamuel Iglesias Gonsalvez2015-10-061-5/+7
| | | | | Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* docs: Mark GL_ARB_enhanced_layouts as in progressTimothy Arceri2015-10-061-1/+7
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* i965: add EXT_polygon_offset_clamp support to gen4/gen5Ilia Mirkin2015-10-057-9/+30
| | | | | Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]>
* meta: Update comment about unsupported texture types.Matt Turner2015-10-051-2/+1
| | | | | | | Ken added support for 2DArray (commit ec23d5197e) and 1DArray (commit 14ca61125) last year. Reviewed-by: Anuj Phogat <[email protected]>
* glx: Drop CRAY support.Matt Turner2015-10-052-102/+0
| | | | | | It couldn't have worked anyway. There were calls to undefined functions. Reviewed-by: Emil Velikov <[email protected]>
* glsl: Remove CSE pass.Matt Turner2015-10-054-475/+0
| | | | | | | | | | | | | | | | With NIR, it actually hurts things. total instructions in shared programs: 6529329 -> 6528888 (-0.01%) instructions in affected programs: 14833 -> 14392 (-2.97%) helped: 299 HURT: 1 In all affected programs I inspected (including the single hurt one) the pass CSE'd some multiplies and caused some reassociation (e.g., caused (A * B) * C to be A * (B * C)) when the original intermediate result was reused elsewhere. Acked-by: Kenneth Graunke <[email protected]>
* i965: Generalize predicated break pass for use in vec4 backend.Matt Turner2015-10-055-12/+16
| | | | | | | instructions in affected programs: 44204 -> 43762 (-1.00%) helped: 221 Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Use backend_instruction in predicated break peephole.Matt Turner2015-10-051-4/+4
| | | | | | | We're not using any fs_inst fields, and the next commit will make the peephole used by the vec4 backend. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Remove SNB embedded-comparison support from optimizations.Matt Turner2015-10-052-32/+3
| | | | | | | | | We never emit IF instructions with an embedded comparison (lost in the switch to NIR), so this code is not used. If we want to readd support, we should have a pass that merges a CMP instruction with an IF or a WHILE instruction after other optimizations have run. Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: Add missing _mm_mfence() before streaming loads.Matt Turner2015-10-051-0/+3
| | | | | | | | | | | | | | | | | According to the Intel Software Development Manual (Volume 1: Basic Architecture, 12.10.3 Streaming Load Hint Instruction): Streaming loads may be weakly ordered and may appear to software to execute out of order with respect to other memory operations. Software must explicitly use fences (e.g. MFENCE) if it needs to preserve order among streaming loads or between streaming loads and other memory operations. That is, a memory fence is needed to preserve the order between the GPU writing the buffer and the streaming loads reading it back. Reported-by: Joseph Nuzman <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Fix intel_miptree_is_fast_clear_capable()Chad Versace2015-10-051-5/+19
| | | | | | | | | | | | | | | | | | | | | | | | There are three types of fast clears: a. fast depth clears b. fast singlesample color clears c. fast multisample color clears Function intel_miptree_is_fast_clear_capable() checks if a miptree supports fast clears of type (b). Rename the function to disambiguate what it does: old: intel_miptree_is_fast_clear_capable new: intel_miptree_supports_non_msrt_fast_clear The functionally accidentally rejected multisampled color surfaces because it thought they were singlesample array surfaces. Fix that by explicitly rejecting surfaces with samples > 1. This fix would have been needed before we enabled layered fast singlesample color clears (introduced in gen8), which we want to do eventually. For now, though, this patch changes no behavior; it just fixes how the driver chooses its behavior. Reviewed-by: Anuj Phogat <[email protected]>
* i965/mt: Declare some functions as staticChad Versace2015-10-052-7/+3
| | | | | | | | intel_tiling_supports_non_msrt_mcs() and intel_miptree_is_fast_clear_capable() are not used outside of intel_mipmap_tree.c. Reviewed-by: Anuj Phogat <[email protected]>
* i965: Make vec4_visitor's destructor virtualIago Toral Quiroga2015-10-051-1/+1
| | | | | | | | | | | | | | | | | | We need a virtual destructor when at least one of the class' methods is virtual. Failure to do so might lead to undefined behavior when destructing derived classes. Fixes the following warning: brw_vec4_gs_visitor.cpp: In function 'const unsigned int* brw::brw_gs_emit(brw_context*, gl_shader_program*, brw_gs_compile*, void*, unsigned int*)': brw_vec4_gs_visitor.cpp:703:11: warning: deleting object of polymorphic class type 'brw::vec4_gs_visitor' which has non-virtual destructor might cause undefined behaviour [-Wdelete-non-virtual-dtor] delete gs; Curro: This shouldn't be causing any actual bugs at the moment because gen6_gs_visitor is the only subclass of vec4_visitor destroyed through a pointer of a base class (vec4_gs_visitor *) and its destructor is basically the same as its parent's. Anyway it seems sensible to change this so it doesn't bite us in the future. Reviewed-by: Francisco Jerez <[email protected]>
* glsl: set glsl error if binding qualifier used on global scopeTapani Pälli2015-10-051-0/+11
| | | | | | | | Fixes following Piglit test: global-scope-binding-qualifier.frag Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Assert on the number of combined UBO and SSBO binding table entriesIago Toral Quiroga2015-10-052-0/+4
| | | | | | | | In theory we can't break this assertion since the compiler frontend checks that we don't exceed any of the individual limits, but it does not hurt to be extra safe. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Reserve binding table space for SSBO surfacesIago Toral Quiroga2015-10-051-0/+1
| | | | | | | These share the space with UBO surfaces but we need to make sure we allocate enough space for both sets (12 of each) Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Define BRW_MAX_SSBOIago Toral Quiroga2015-10-052-7/+10
| | | | | | Instead of using hard-coded values. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Define BRW_MAX_UBOIago Toral Quiroga2015-10-052-3/+6
| | | | | | Instead of using hard-coded values. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Remove more dead visitor/vertex program code.Matt Turner2015-10-043-23/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Don't print line numbers with INTEL_DEBUG=optimizer.Matt Turner2015-10-041-2/+4
| | | | | | | The thing you want to do with the output files is diff them, which is made more difficult by line numbers changing. Reviewed-by: Alejandro Piñeiro <[email protected]>
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