summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* doc: Set GL_OES_geometry_shader as startedMarta Lofstedt2015-11-301-1/+1
| | | | | Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* gles2: Update gl2ext.h to revision: 32120Marta Lofstedt2015-11-301-6/+934
| | | | | | | | | This is needed to be able to implement the accepted OES extensions. Cc: "11.0 11.1" <[email protected]> Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* vl/buffers: fixes vl_video_buffer_formats for RGBXJulien Isorce2015-11-301-1/+1
| | | | | | | Fixes: 42a5e143a8d "vl/buffers: add RGBX and BGRX to the supported formats" Cc: [email protected] Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965/fs: remove unused fs_reg offsetSamuel Iglesias Gonsálvez2015-11-301-1/+0
| | | | | Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Abdiel Janulgue <[email protected]>
* i965: Add src/dst interference for certain instructions with hazards.Kenneth Graunke2015-11-307-35/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When working on tessellation shaders, I created some vec4 virtual opcodes for creating message headers through a sequence like: mov(8) g7<1>UD 0x00000000UD { align1 WE_all 1Q compacted }; mov(1) g7.5<1>UD 0x00000100UD { align1 WE_all }; mov(1) g7<1>UD g0<0,1,0>UD { align1 WE_all compacted }; mov(1) g7.3<1>UD g8<0,1,0>UD { align1 WE_all }; This is done in the generator since the vec4 backend can't handle align1 regioning. From the visitor's point of view, this is a single opcode: hs_set_output_urb_offsets vgrf7.0:UD, 1U, vgrf8.xxxx:UD Normally, there's no hazard between sources and destinations - an instruction (naturally) reads its sources, then writes the result to the destination. However, when the virtual instruction generates multiple hardware instructions, we can get into trouble. In the above example, if the register allocator assigned vgrf7 and vgrf8 to the same hardware register, then we'd clobber the source with 0 in the first instruction, and read back the wrong value in the last one. It occured to me that this is exactly the same problem we have with SIMD16 instructions that use W/UW or B/UB types with 0 stride. The hardware implicitly decodes them as two SIMD8 instructions, and with the overlapping regions, the first would clobber the second. Previously, we handled that by incrementing the live range end IP by 1, which works, but is excessive: the next instruction doesn't actually care about that. It might also be the end of control flow. This might keep values alive too long. What we really want is to say "my source and destinations interfere". This patch creates new infrastructure for doing just that, and teaches the register allocator to add interference when there's a hazard. For my vec4 case, we can determine this by switching on opcodes. For the SIMD16 case, we just move the existing code there. I audited our existing virtual opcodes that generate multiple instructions; I believe FS_OPCODE_PACK_HALF_2x16_SPLIT needs this treatment as well, but no others. v2: Rebased by mattst88. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Fix JIP to properly skip over unrelated control flow.Kenneth Graunke2015-11-301-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've apparently always been botching JIP for sequences such as: do cmp.f0.0 ... (+f0.0) break ... if ... else ... endif ... while Normally, UIP is supposed to point to the final destination of the jump, while in nested control flow, JIP is supposed to point to the end of the current nesting level. It essentially bounces out of the current nested control flow, to an instruction that has a JIP which bounces out another level, and so on. In the above example, when setting JIP for the BREAK, we call brw_find_next_block_end(), which begins a search after the BREAK for the next ENDIF, ELSE, WHILE, or HALT. It ignores the IF and finds the ELSE, setting JIP there. This makes no sense at all. The break is supposed to skip over the whole if/else/endif block entirely. They have a sibling relationship, not a nesting relationship. This patch fixes brw_find_next_block_end() to track depth as it does its search, and ignore anything not at depth 0. So when it sees the IF, it ignores everything until after the ENDIF. That way, it finds the end of the right block. I noticed this while reading some assembly code. We believe jumping earlier is harmless, but makes the EU walk through a bunch of disabled instructions for no reason. I noticed that GLBenchmark Manhattan had a shader that contained a BREAK with a bogus JIP, but didn't measure any performance improvement (it's likely miniscule, if there is any). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* r600: move per-type settings into a switch statementDave Airlie2015-11-301-5/+13
| | | | | | | This will allow adding tess stuff much cleaner later. Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: split out common alu_writes pattern.Dave Airlie2015-11-301-7/+12
| | | | | | | | This just splits out a common pattern into an inline function to make things cleaner to read. Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/llvm: fix r600/llvm buildDave Airlie2015-11-301-1/+1
| | | | | | Reported on irc by gryffus Signed-off-by: Dave Airlie <[email protected]>
* r600: fixes for register definitions.Dave Airlie2015-11-301-3/+3
| | | | | | Forgot to add these. Signed-off-by: Dave Airlie <[email protected]>
* r600: add missing register to initial stateDave Airlie2015-11-303-7/+15
| | | | | | | | | | We really should initialise HS/LS_2 and SQ_LDS_ALLOC exists on all evergreen not just cayman, so we should initialise it as well. Reviewed-by: Glenn Kennard <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: define registers required for tessellationDave Airlie2015-11-302-27/+113
| | | | | | | | | This adds the defines for a bunch of registers and shader values that are required to implement tessellation. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: consolidate clip state updatesDave Airlie2015-11-302-17/+16
| | | | | | | | Move some common code into one place, tess will also need to use this function. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nv50/ir: always display the opcode number for unknown instructionsSamuel Pitoiset2015-11-292-2/+2
| | | | | | | This helps in debugging unknown instructions. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: remove len argument from _mesa_shader_debug()Emil Velikov2015-11-295-10/+9
| | | | | | | | | | There was only a single user which was using strlen(buf). As this function is not user facing (i.e. we don't need to feed back original length via a callback), we can simplify things. Suggested-by: Timothy Arceri <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* drivers/x11: scons: partially revert b9b40ef9b76Emil Velikov2015-11-291-2/+0
| | | | | | | | | | As glsl_types.{cpp,h} were moved out of the sconscript (commit b23a4859f4d "scons: Build nir/glsl_types.cpp once.") remove the dangling includes. Cc: Jose Fonseca <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* nir: remove recursive inclusion in builtin_type_macros.hEmil Velikov2015-11-291-2/+0
| | | | | | | The header is already included by glsl_types.{cpp,h}. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: remove unneeded includeEmil Velikov2015-11-291-1/+0
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa/program: remove dead function declarationsEmil Velikov2015-11-292-5/+0
| | | | | | | | | | | | Dead since 5e9aa9926b9 (2011) - _mesa_ir_compile_shader 69e07bdeb42 (2009) - _mesa_get_program_register Cc: Kenneth Graunke <[email protected]> Cc: Brian Paul <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* auxiliary/vl/dri: fd management cleanupsEmil Velikov2015-11-291-2/+5
| | | | | | | | | | Analogous to previous commit, minus the extra dup. We are the one opening the device thus we can directly use the fd. Spotted by Coverity (CID 1339867, 1339877) Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]>
* auxiliary/vl/drm: fd management cleanupsEmil Velikov2015-11-291-1/+7
| | | | | | | | | Analogous to previous commit. Spotted by Coverity (CID 1339868) Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]>
* st/xa: fd management cleanupsEmil Velikov2015-11-291-1/+8
| | | | | | | | | Analogous to previous commit. Spotted by Coverity (CID 1339866) Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]>
* st/dri: fd management cleanupsEmil Velikov2015-11-291-2/+14
| | | | | | | | | | | Add some checks if the original/dup'd fd is valid and ensure that we don't leak it on error. The former is implicitly handled within the pipe_loader, although let's make things explicit and check beforehand. Spotted by Coverity (CID 1339865) Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]>
* pipe-loader: check if winsys.name is non-null prior to strcmpEmil Velikov2015-11-291-4/+4
| | | | | | | | | | | | In theory this wouldn't be an issue, as we'll find the correct name and break out of the loop before we hit the sentinel. Let's fix this and avoid issues in the future. Spotted by Coverity (CID 1339869, 1339870, 1339871) Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]>
* st/va: add missing break statementEmil Velikov2015-11-291-0/+1
| | | | | | | | | | | | | | Earlier commit factored out the mpeg4 IQ matrix handling into separate function, although it forgot to add a break in its case statement. Thus the data ended up partially overwritten as the mpeg4 and h265 structs are members of the desc union. Spotted by Coverity (CID 1341052) Fixes: 64761a841db "st/va: move MPEG4 functions into separate file" Cc: Julien Isorce <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Christian König <[email protected]>
* mesa: support GL_RED/GL_RG in ES2 contexts when driver support existsIlia Mirkin2015-11-284-4/+11
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93126 Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]> Cc: "11.0 11.1" <[email protected]>
* radeon: only suspend queries on flush if they haven't been suspended yetNicolai Hähnle2015-11-282-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Non-timer queries are suspended during blits. When the blits end, the queries are resumed, but this resume operation itself might run out of CS space and trigger a flush. When this happens, we must prevent a duplicate suspend during preflush suspend, and we must also prevent a duplicate resume when the CS flush returns back to the original resume operation. This fixes a regression that was introduced by: commit 8a125afa6e88a3eeddba8c7fdc1a75c9b99d5489 Author: Nicolai Hähnle <[email protected]> Date: Wed Nov 18 18:40:22 2015 +0100 radeon: ensure that timing/profiling queries are suspended on flush The queries_suspended_for_flush flag is redundant because suspended queries are not removed from their respective linked list. Reviewed-by: Marek Olšák <[email protected]> Reported-by: Axel Davy <[email protected]> Cc: "11.1" <[email protected]> Tested-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* scons: Use LD version script for libgl-xlib.Jose Fonseca2015-11-271-2/+6
| | | | Trivial.
* svga: Don't return value from void function.Jose Fonseca2015-11-271-1/+2
| | | | | | | Addresses MSVC warning C4098: 'svga_destroy_query' : 'void' function returning a value. Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: Make pipe_query_result::batch array length non-zero.Jose Fonseca2015-11-271-2/+2
| | | | | | | | | | | | Zero length arrays are non standard: warning C4200: nonstandard extension used : zero-sized array in struct/union Cannot generate copy-ctor or copy-assignment operator when UDT contains a zero-sized array And all code does `N * sizeof query_result->batch[0]`, so it should work exactly the same. Reviewed-by: Roland Scheidegger <[email protected]>
* util: Tiny optimisation for the linear→srgb conversionNeil Roberts2015-11-271-1/+1
| | | | | | When converting 0.0 it would be nice if it didn't do any arithmetic. Reviewed-by: Jason Ekstrand <[email protected]>
* docs: Update GL3.txt to add ARB_internalformat_query2Eduardo Lima Mitev2015-11-261-1/+1
| | | | | | | | | | | | | Added to OpenGL 4.3 section, tagged as 'in progress (elima)'. See https://bugs.freedesktop.org/show_bug.cgi?id=92687. Thanks to Thomas H.P. Andersen for remainding me about this. v1: - Update the already existing entry in section 4.3 instead (Ilia Mirkin). - Added my BZ nickname as contact person (Felix Schwarz). Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: don't generate extra errors in ValidateProgramPipelineTimothy Arceri2015-11-271-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | From Section 11.1.3.11 (Validation) of the GLES 3.1 spec: "An INVALID_OPERATION error is generated by any command that trans- fers vertices to the GL or launches compute work if the current set of active program objects cannot be executed, for reasons including:" It then goes on to list the rules we validate in the _mesa_validate_program_pipeline() function. For ValidateProgramPipeline the only mention of generating an error is: "An INVALID_OPERATION error is generated if pipeline is not a name re- turned from a previous call to GenProgramPipelines or if such a name has since been deleted by DeleteProgramPipelines," Which we handle separately. This fixes: ES31-CTS.sepshaderobjs.PipelineApi No regressions on the eEQP 3.1 tests. Cc: Gregory Hainaut <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* freedreno/ir3: assign varying locations laterRob Clark2015-11-264-29/+37
| | | | | | | | | | | | | Rather than assigning inloc up front, when we don't yet know if it will be unused, assign it last thing before the legalize pass. Also, realize when inputs are unused (since for frag shader's we can't rely on them being removed from ir->inputs[]). This doesn't make sense if we don't also dynamically assign the inloc's, since we could end up telling the hw the wrong # of varyings (since we currently assume that the # of varyings and max-inloc are related..) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use instr flag to mark unused instructionsRob Clark2015-11-264-14/+24
| | | | | | Rather than magic depth value, which won't be available in later stages. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: rework vinterp/vpsreplRob Clark2015-11-261-12/+36
| | | | | | Same as previous commit, for a4xx. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: rework vinterp/vpsreplRob Clark2015-11-261-12/+37
| | | | | | | | | | | | Make the interpolation / point-sprite replacement mode setup deal with varying packing. In a later commit, we switch to packing just the varying components that are actually used by the frag shader, so we won't be able to assume everything is vec4's aligned to vec4. Which would highly confuse the previous vinterp/vpsrepl logic. Signed-off-by: Rob Clark <[email protected]>
* clover: fix tgsi compiler crash with invalid srcSerge Martin2015-11-261-0/+5
| | | | Reviewed-by: Francisco Jerez <[email protected]>
* i965/gen9+: Switch thread scratch space to non-coherent stateless access.Francisco Jerez2015-11-263-4/+19
| | | | | | | | | | | | | | | | | | | | The thread scratch space is thread-local so using the full IA-coherent stateless surface index (255 since Gen8) is unnecessary and potentially expensive. On Gen8 and early steppings of Gen9 this is not a functional change because the kernel already sets bit 4 of HDC_CHICKEN0 which overrides all HDC memory access to be non-coherent in order to workaround a hardware bug. This happens to fix a full system hang when running any spilling code on a pre-production SKL GT4e machine I have on my desk (forcing all HDC access to non-coherent from the kernel up to stepping F0 might be a good idea though regardless of this patch), and improves performance of the OglPSBump2 SynMark benchmark run with INTEL_DEBUG=spill_fs by 33% (11 runs, 5% significance) on a production SKL GT2 (on which HDC IA-coherency is apparently functional so it wouldn't make sense to disable globally). Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/fs: Don't use Gen7-style scratch block reads on Gen9+.Francisco Jerez2015-11-261-2/+9
| | | | | | | | | | | | | Unfortunately Gen7 scratch block reads and writes seem to be hardwired to BTI 255 even on Gen9+ where that index causes the dataport to do an IA-coherent read or write. This change is required for the next patch to be correct, since otherwise we would be writing to the scratch space using non-coherent access and then reading it back using IA-coherent reads, which wouldn't be guaranteed to return the value previously written to the same location without introducing an additional HDC flush in between. Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Add symbolic defines for some magic dataport surface indices.Francisco Jerez2015-11-261-0/+13
| | | | Reviewed-by: Kristian Høgsberg <[email protected]>
* radeon: use PIPE_DRIVER_QUERY_FLAG_DONT_LIST for perfcountersNicolai Hähnle2015-11-261-0/+2
| | | | | | | | Since the query names are not very enlightening, and there are thousands of them, GALLIUM_HUD=help should only show the first and last query name for each hardware block. Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_DRIVER_QUERY_FLAG_DONT_LISTNicolai Hähnle2015-11-262-1/+12
| | | | | | | This allows the driver to give a hint to the HUD so that GALLIUM_HUD=help is less spammy. Reviewed-by: Marek Olšák <[email protected]>
* radeon: delay the generation of driver query names until first useNicolai Hähnle2015-11-263-104/+113
| | | | | | | This shaves a bit more time off the startup of programs that don't actually use performance counters. Reviewed-by: Marek Olšák <[email protected]>
* st/va: add missing profiles in PipeToProfile's switch.Julien Isorce2015-11-261-0/+7
| | | | | | | Otherwise assert is raised from vlVaQueryConfigProfiles's for loop. Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Christian König <[email protected]>
* mesa: remove ARB_geometry_shader4Marta Lofstedt2015-11-2611-141/+9
| | | | | | | | | | No drivers currently implement ARB_geometry_shader4, nor are there any plans to implement it. We only support the version of geometry shaders that was incorporated into OpenGL 3.2 / GLSL 1.50. Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: error out in indirect draw when vertex bindings mismatchTapani Pälli2015-11-263-0/+27
| | | | | | | | | | | | | | | | | | | | Patch adds additional mask for tracking which vertex arrays have associated vertex buffer binding set. This array can be directly compared to which vertex arrays are enabled and should match when drawing. Fixes following CTS tests: ES31-CTS.draw_indirect.negative-noVBO-arrays ES31-CTS.draw_indirect.negative-noVBO-elements v2: update mask in vertex_array_attrib_binding v3: rename mask and make it track _BoundArrays which matches what was actually originally wanted (Fredrik Höglund) v4: code cleanup, check for GLES 3.1 (Fredrik Höglund) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Fredrik Höglund <[email protected]>
* targets/xvmc: use the non-inline sw helpersMichel Dänzer2015-11-261-0/+1
| | | | | | | | | | | | | | | This was missed in commit 59cfb21d ("targets: use the non-inline sw helpers"). Fixes build failure: CXXLD libXvMCgallium.la ../../../../src/gallium/auxiliary/pipe-loader/.libs/libpipe_loader_static.a(libpipe_loader_static_la-pipe_loader_sw.o):(.data.rel.ro+0x0): undefined reference to `sw_screen_create' collect2: error: ld returned 1 exit status Makefile:756: recipe for target 'libXvMCgallium.la' failed make[3]: *** [libXvMCgallium.la] Error 1 Trivial.
* targets/nine: remove freedreno targetEmil Velikov2015-11-251-3/+0
| | | | | | | | Analogous to previous commit. As we no longer have anyone who uses NIR we can drop the link. Signed-off-by: Emil Velikov <[email protected]> Acked-by: Rob Clark <[email protected]>
* targets/nine: remove vc4 targetEmil Velikov2015-11-251-2/+0
| | | | | | | There are no users for it. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 21:13:54 +0000