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* freedreno/ir3: stop hard-coding FS input regsRob Clark2018-08-147-183/+103
| | | | | | | | | | We originally did this because at the time we didn't know all the bitfields to configure where various frag shader sysval's went. But we do. So switch to using sysvals for all the frag shader inputs. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use r63.x for unused inputsRob Clark2018-08-141-3/+3
| | | | | | | This way, unused sysval inputs, like frag_vcoord, get the correct regid value to disable the input. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: create all inputs in first blockRob Clark2018-08-141-17/+17
| | | | | | | | create_input()/create_input_compmask() should take the ctx as arg, rather than block, to enforce that all inputs are created in the first block, so that RA sees them as live at the start of the shader. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: rename s/frag_pos/frag_vcoord/gRob Clark2018-08-142-17/+22
| | | | | | | Make it more clear that this is varying fetch related. Also fixup some comments. Just cleanup for next patches. Signed-off-by: Rob Clark <[email protected]>
* compiler: add SYSTEM_VALUE_VARYING_COORDRob Clark2018-08-143-0/+8
| | | | | | | | Used internally in freedreno/ir3 for the vec2 value that hw passes to shader to use as coordinate for bary.f (varying fetch) instruction. This is not the same as SYSTEM_VALUE_FRAG_COORD. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move per-generation compiler configRob Clark2018-08-143-43/+52
| | | | | | | Move it from the compile ctx to the compiler object, before adding new things for a6xx. Signed-off-by: Rob Clark <[email protected]>
* radv: Update to new VK_EXT_vertex_attribute_divisor to version 2.Bas Nieuwenhuizen2018-08-142-4/+5
| | | | | | | | | | | | | Behavior wrt firstInstance got changed, and a divisor of 0 has been disallowed. The new version of the ext got published in specification 1.1.81. Sending to stable since the only known user is DXVK, which needs this for correctness. Reviewed-by: Samuel Pitoiset <[email protected]> CC: 18.2 <[email protected]>
* radv: Allow ETC2 on RAVEN and VEGA10 instead of all GFX9.Bas Nieuwenhuizen2018-08-141-1/+2
| | | | | | | Follow radeonsi. Fixes: 3665f66ef26 "radv: Add support for ETC2 textures." Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Fix missing Android platform define.Bas Nieuwenhuizen2018-08-142-1/+3
| | | | | CC: <[email protected]> Acked-by: Samuel Pitoiset <[email protected]>
* freedreno: move free() into fdN_context_destroy()Rob Clark2018-08-145-2/+7
| | | | | | | | Following patches will be doing further cleanup after calling fd_context_destroy() so it is easier if we move the free() into the per-gen backend code. Signed-off-by: Rob Clark <[email protected]>
* freedreno: a2xx: ir2 updateJonathan Marek2018-08-145-545/+615
| | | | | | | | | | | | | | | | | | | this patch brings a number of changes to ir2: -ir2 now generates CF clauses as necessary during assembly. this simplifies fd2_program/fd2_compiler and is necessary to implement optimization passes -ir2 now has separate vector/scalar instructions. this will make it easier to implementing scheduling of scalar+vector instructions together. dst_reg is also now seperate from src registers instead of a single list -ir2 now implements register allocation. this makes it possible to compile shaders which have more than 64 TGSI registers -ir2 now implements the following optimizations: removal of IN/OUT MOV instructions generated by TGSI and removal of unused instructions when some exports are disabled -ir2 now allows full 8-bit index for constants -ir2_alloc no longer allocates 4 times too many bytes Signed-off-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* docs: update calendar 18.2.0-rc1 and 18.2.0-rc2 are outAndres Gomez2018-08-141-13/+1
| | | | Signed-off-by: Andres Gomez <[email protected]>
* radv: Add on-demand compilation of built-in shaders.Bas Nieuwenhuizen2018-08-1413-80/+454
| | | | | | | | | | | | | | | | | | | | | | | | | In environments where we cannot cache, e.g. Android (no homedir), ChromeOS (readonly rootfs) or sandboxes (cannot open cache), the startup cost of creating a device in radv is rather high, due to compiling all possible built-in pipelines up front. This meant depending on the CPU a 1-4 sec cost of creating a Device. For CTS this cost is unacceptable, and likely for starting random apps too. So if there is no cache, with this patch radv will compile shaders on demand. Once there is a cache from the first run, even if incomplete, the driver knows that it can likely write the cache and precompiles everything. Note that I did not switch the buffer and itob/btoi compute pipelines to on-demand, since you cannot really do anything in Vulkan without them and there are only a few. This reduces the CTS runtime for the no caches scenario on my threadripper from 32 minutes to 8 minutes. Reviewed-by: Dave Airlie <[email protected]>
* radv: Refactor blit pipeline creation.Bas Nieuwenhuizen2018-08-141-350/+175
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Make fs key exemplars ordered to be a reverse fs_key lookup.Bas Nieuwenhuizen2018-08-147-88/+39
| | | | | | | While at it, share the exemplars and account for a non-occurring fs key. Reviewed-by: Dave Airlie <[email protected]>
* virgl: ARB_texture_barrier supportDave Airlie2018-08-147-4/+25
| | | | Reviewed-by: Tomeu Vizoso <[email protected]>
* docs: update calendar, add news item and link release notes for 18.1.6Dylan Baker2018-08-132-7/+2
| | | | Signed-off-by: Dylan Baker <[email protected]>
* docs: Add sha256 sums for 18.1.6Dylan Baker2018-08-131-1/+2
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* docs: Add release notes for 18.1.6Dylan Baker2018-08-131-0/+187
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* mesa/glspirv: fix compilation with MSVCAlejandro Piñeiro2018-08-131-1/+1
| | | | | | | From AppVeyor #8582, it seems that MSVC doesn't like uint, so this patch replaces it with unsigned. Reviewed-by: Roland Scheidegger <[email protected]>
* travis: install correct version of mako for each build systemEric Engestrom2018-08-131-2/+7
| | | | | | | | | Meson now uses python3, so let's add a block for Autotools, move that line into the buildsys-specific blocks, and set the correct version for Meson. Fixes: 2ee1c86d71bee5ddca2c "meson: Build with Python 3" Signed-off-by: Eric Engestrom <[email protected]>
* mesa/st/glsl_to_tgsi: fixup copy-paste mistakeErik Faye-Lund2018-08-131-1/+1
| | | | | | | | | | | | | This is clearly a copy-paste error; if we validate the reladdr2-pointer, we don't want to traverse to the reladdr-pointer. Especially since the check above shows that reladdr could be NULL here. Noticed by Coverity. CID: 1438389, 1438390 Fixes: 568bda2f2d3 ("mesa/st/glsl_to_tgsi: Split arrays whose elements are only accessed directly") Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gert Wollny <[email protected]>
* i965/nir: Use the nir copy of shader_info to handle gl_PatchVerticesInNeil Roberts2018-08-131-1/+1
| | | | | | | | | | | | | | | | | | Instead of using the copy of shader_info stored in gl_program, it now uses the one in nir_shader. This is needed for SPIR-V because the info.tess.tcs_vertices_out is filled in via _mesa_spirv_to_nir which happens much later than with a GLSL shader. The copy of shader_data in gl_program is only updated later via brw_shader_gather_info but that is too late. For GLSL this shouldn't create any problems because the nir copy of the shader_info is immediately copied from the gl_program in glsl_to_nir. v2: updated after commit "i965: Combine both gl_PatchVerticesIn lowering passes." (488972) (Alejandro Piñeiro) Reviewed-by: Timothy Arceri <[email protected]>
* mesa/glspirv: Set separate_shader on shader_infoNeil Roberts2018-08-131-0/+2
| | | | | | | | | The value is copied from the gl_program. If we don’t do this then it will get reset back to zero in brw_shader_gather_info. This isn’t a problem for GLSL because in that case the nir_shader is initialised with a copy of the shader_info from the gl_program. Reviewed-by: Timothy Arceri <[email protected]>
* mesa/glspirv: pick off the only entry point we needIago Toral Quiroga2018-08-131-0/+15
| | | | | | | | | This is the same we do for vulkan drivers This is needed to pass the following CTS test: KHR-GL45.gl_spirv.spirv_modules_shader_binary_multiple_shader_objects_test Reviewed-by: Timothy Arceri <[email protected]>
* mesa/glspirv: compute double inputs and remap attributesAlejandro Piñeiro2018-08-131-0/+19
| | | | | | | | | | | | | | input locations used by input attributes are not handled in the same way in OpenGL vs Vulkan. There is a detailed explanation of such differences on the following commit: c2acf97fcc9b32eaa9778771282758e5652a8ad4 So with this commit, the same adjustment that is done after glsl_to_nir, is being done after spirv_to_nir, when it is used on OpenGL (ARB_gl_spirv). Reviewed-by: Timothy Arceri <[email protected]>
* nir/glsl: make nir_remap_attributes publicAlejandro Piñeiro2018-08-133-17/+27
| | | | | | As we plan to reuse it for ARB_gl_spirv implementation. Reviewed-by: Timothy Arceri <[email protected]>
* nir/lower_samplers: don't assume a deref for both texture and sampler srcsAlejandro Piñeiro2018-08-131-53/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After commit "nir: Use derefs in nir_lower_samplers" (75286c2d083cdbdfb202a93349e567df0441d5f7) assumes one deref for both the texture and the sampler. However there are cases (on OpenGL, using ARB_gl_spirv) where SPIR-V is not providing a sampler, like for texture query levels ops. Although we could make spirv_to_nir to provide a sampler deref for those cases, it is not really needed, and wrong from the Vulkan point of view. This patch fixes the following (borrowed) tests run on SPIR-V mode: arb_compute_shader/execution/basic-texelFetch.shader_test arb_gpu_shader5/execution/sampler_array_indexing/fs-simple-texture-size.shader_test arb_texture_query_levels/execution/fs-baselevel.shader_test arb_texture_query_levels/execution/fs-maxlevel.shader_test arb_texture_query_levels/execution/fs-miptree.shader_test arb_texture_query_levels/execution/fs-nomips.shader_test arb_texture_query_levels/execution/vs-baselevel.shader_test arb_texture_query_levels/execution/vs-maxlevel.shader_test arb_texture_query_levels/execution/vs-miptree.shader_test arb_texture_query_levels/execution/vs-nomips.shader_test glsl-1.30/execution/fs-textureSize-compare.shader_test v2: merge lower_tex_src_to_offset and calc_sampler_offsets together, update texture/sampler index and texture_array_size directly on lower_tex_src_to_offset (Jason) v3: clarify one comment (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* nir/linker: take into account hidden uniformsAlejandro Piñeiro2018-08-132-1/+8
| | | | | | | | | | | | | | | | | | | | | So they are not exposed through the introspection API. It is worth to note that the number of hidden uniforms of GLSL linking vs SPIR-V linking would be somewhat different due the differen order of the nir lowerings/optimizations. For example: gl_FbWposYTransform. This is introduced as part of nir_lower_wpos_ytransform. On GLSL that is executed after the IR-based linking. So that means that on GLSL the UniformStorage will not include this uniform. With the SPIR-V linking, that uniform is already present, but marked as hidden. So it will be included on the UniformStorage, but as hidden. One alternative would create a special how_declared for that case, but seemed an overkill. Using hidden should be ok as far as it is used properly. Reviewed-by: Timothy Arceri <[email protected]>
* nir: add how_declared to nir_variable.dataAlejandro Piñeiro2018-08-133-1/+26
| | | | | | | | | Equivalent to the already existing how_declared at GLSL IR. The only difference is that we are not adding all the declaration_type available on GLSL, only the one that we will use on the short term. We would add more mode if needed on the future. Reviewed-by: Timothy Arceri <[email protected]>
* spirv: Make VertexIndex and VertexId both non-zero-basedNeil Roberts2018-08-131-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | GLSL has gl_VertexID which is supposed to be non-zero-based. SPIR-V has both VertexIndex and VertexId builtins whose meanings are defined by the APIs. Vulkan defines VertexIndex as being non-zero-based. In Vulkan VertexId and InstanceId have no meaning and are pretty much just reserved for OpenGL at this point. GL_ARB_spirv removes VertexIndex and defines VertexId to be the same as gl_VertexId (which is also non-zero-based). Previously in Mesa it was treating VertexIndex as non-zero-based and VertexId as zero-based, so it was breaking for GL. This behaviour was apparently based on Khronos bug 14255. However that bug doesn’t seem to have made a final decision for VertexId. Assuming there really is no other definition for VertexId for Vulkan it seems better to just make them both have the same value. v2: update comment and commit descriptions, based on Jason Ekstrand explanation of the meaning/rationale behind all those builtins (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: fill info.gs.input_primitive tooAlejandro Piñeiro2018-08-131-0/+2
| | | | | | | | | | | info.gs.output_primitive was already being filled. Not sure why this is not needed on Vulkan, but we found to be needed for ARB_gl_spirv. Specifically, this is needed to get the following test passing: KHR-GL45.gl_spirv.spirv_validation_builtin_variable_decorations_test Reviewed-by: Timothy Arceri <[email protected]>
* docs/features: mark GL_EXT_render_snorm as done for i965Tapani Pälli2018-08-131-0/+1
| | | | Signed-off-by: Tapani Pälli <[email protected]>
* i965: enable EXT_render_snormTapani Pälli2018-08-131-0/+1
| | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* mesa: enable EXT_render_snorm extensionTapani Pälli2018-08-136-9/+61
| | | | | | | | | | | | | | | | Patch sets additional formats renderable and enables the extension when OpenGL ES 3.1 is supported. v2: instead of dummy_true, have a separate toggle for extension (Eric Anholt) v3: add missing checks, simplify some existing checks and fix glCopyTexImage2D check (Nanley Chery) add SHORT and BYTE support in read_pixels_es3_error_check Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* blorp: Properly handle Z24X8 blits.Kenneth Graunke2018-08-112-12/+11
| | | | | | | | | | | | | | | | | | | One of the reasons we didn't notice that R24_UNORM_X8_TYPELESS destinations were broken was that an earlier layer was swapping it out for B8G8R8A8_UNORM. That made Z24X8 -> Z24X8 blits work. However, R32_FLOAT -> R24_UNORM_X8_TYPELESS was still totally broken. The old code only considered one format at a time, without thinking that format conversion may need to occur. This patch moves the translation out to a place where it can consider both formats. If both are Z24X8, we continue using B8G8R8A8_UNORM to avoid having to do shader math workarounds. If we have a Z24X8 destination, but a non-matching source, we use our shader hacks to actually render to it properly. Fixes: 804856fa5735164cc0733ad0ea62adad39b00ae2 (intel/blorp: Handle more exotic destination formats) Reviewed-by: Jason Ekstrand <[email protected]>
* blorp: Don't try to use R32_UNORM for R24_UNORM_X8_TYPELESS rendering.Kenneth Graunke2018-08-111-5/+5
| | | | | | | | | | | | | The hardware doesn't support rendering to R24_UNORM_X8_TYPELESS, so Jason decided to fake it with a bit of shader math and R32_UNORM RTs. The only problem is that R32_UNORM isn't renderable either...so we've just traded one bad format for another. This patch makes us use R32_UINT instead. Fixes: 804856fa5735164cc0733ad0ea62adad39b00ae2 (intel/blorp: Handle more exotic destination formats) Reviewed-by: Jason Ekstrand <[email protected]>
* intel: Switch the order of the 2x MSAA sample positionsJason Ekstrand2018-08-114-14/+24
| | | | | | | | The Vulkan 1.1.82 spec flipped the order to better match D3D. Cc: [email protected] Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* mesa/st/tests: Add array life range estimation and renumbering testsGert Wollny2018-08-111-0/+211
| | | | | Signed-off-by: Gert Wollny <[email protected]> Acked-by: Dave Airlie <[email protected]>
* mesa/st/tests: Add array life range tests infrastructure to common test classGert Wollny2018-08-112-27/+186
| | | | | Signed-off-by: Gert Wollny <[email protected]> Acked-by: Dave Airlie <[email protected]>
* mesa/st/glsl_to_tgsi: Expose array live range tracking and mergingGert Wollny2018-08-115-17/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch ties in the array split, merge, and interleave code. shader-db changes in the TGSI code are: original code | array-merge | change mean max | mean max | best mean % worst ----------------------------------------------------------- arrays 0.05 2 | 0.00 0 | -2 -100 0 total temps 5.05 21 | 4.92 20 | -15 -2.59 1 instr 55.33 988 | 55.20 988 | -15 -0.24 0 Evaluation: Run shader-db in single thread mode (otherwise the output is not ordered and the best and worst column don't make sense) to get results pre-stats.txt and post-stats.txt. Then using python pandas: import pandas as pd old_stats = pd.read_csv('pre-stats.txt') new_stats = pd.read_csv('post-stats.txt') omean = old_stats.mean() omax = old_stats.max() nmean = new_stats.mean() nmax = new_stats.max() delta = new_stats - old_stats pd.concat([omean, omax, nmean, nmax, delta.min(), delta.mean()/old_stats.mean()*100, delta.max()], axis=1, keys=['mean', 'max', 'mean', 'max', 'best', 'avg change %', 'worst']) v4: - Correct typo and add bugs that are fixed by this series. - Update stats and describe stats evaluation Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105371 https://bugs.freedesktop.org/show_bug.cgi?id=100200 Signed-off-by: Gert Wollny <[email protected]> Acked-by: Dave Airlie <[email protected]>
* mesa/st/glsl_to_tgsi: add array life range evaluation into tracking codeGert Wollny2018-08-111-12/+50
| | | | | | | | v4: Also track the register given in inst->resource. (thanks: Benedikt Schemmer for testing the patches on radeonsi, which revealed that I was missing tracking this) Signed-off-by: Gert Wollny <[email protected]> Acked-by: Dave Airlie <[email protected]>
* mesa/st/glsl_to_tgsi: add class for array access trackingGert Wollny2018-08-111-0/+102
| | | | | | | | | | | | | | | | | | Because of the indirect access it is impossible to obtain an accurate per component and array element tracking. Therefore, the tracking is simplified to only track whether any element was accessed, whether this happend conditionally in a loop. In addition, while tracking of temporaries requires a per-componet tracking that is later fused, for arrays only the components access mask is neede. The resulting tracking code and evaluation of the array live range is sufficiently different from the evaluation of the live range of temporaries to justify implementing this in a different class instead of adding more complexity to the already existing code for temporary life range evaluation. v4: Update commit message to make it clearer why this class is seperate from the tracking of temporaries. Signed-off-by: Gert Wollny <[email protected]> Acked-by: Dave Airlie <[email protected]>
* mesa/st/glsl_to_tgsi: move evaluation of read mask up in the call hierarchyGert Wollny2018-08-111-7/+8
| | | | | | | | | In preparation of the array live range tracking the evaluation of the read mask is moved out the register live range tracking to the enclosing call of the generalized read access tracking. Signed-off-by: Gert Wollny <[email protected]> Acked-by: Dave Airlie <[email protected]>
* mesa/st/glsl_to_tgsi: rename access_record to register_merge_record and some ↵Gert Wollny2018-08-112-32/+33
| | | | | | | | | | | more renames In preparartion of adding the tracking of the live range the classes that refer to temporary registers are renamed. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Gert Wollny <[email protected]> Acked-by: Dave Airlie <[email protected]>
* mesa/st/tests: Add tests for array merge helper classes.Gert Wollny2018-08-114-7/+787
| | | | | | | | | | v2: - Define tests also in the meson.build file. v4: - Check no-op mapping of all bits. - Convert tests to the new class layout used in the merge evaulation. - remove dependency on llvm in meson build (Thanks Dylan Baker for pointing out that this might not needed) Signed-off-by: Gert Wollny <[email protected]> Acked-by: Dave Airlie <[email protected]>
* mesa/st/glsl_to_tgsi: Add array merge logicGert Wollny2018-08-112-2/+407
| | | | | | | v4: - Update the code to use the new merge logic. - Use a cleaner, class-based approach for the evaluation of merges. Signed-off-by: Gert Wollny <[email protected]> Acked-by: Dave Airlie <[email protected]>
* mesa/st/glsl_to_tgsi: Add helper classes to apply array merging and interleavingGert Wollny2018-08-112-1/+164
| | | | | | | | | v4: - Remove logic for evaluation of swizzles and merges since this was moved to array_live_range. This class now only handles the actual remapping. Signed-off-by: Gert Wollny <[email protected]> Acked-by: Dave Airlie <[email protected]>
* mesa/st/glsl_to_tgsi: Add helper class for array live range merging and ↵Gert Wollny2018-08-114-0/+319
| | | | | | | | | | | | | | | | | interleaving This class holds the array length, live range, and accessed components, and it implements the logic for evaluating how arrays are merged and interleaved. v4: - Add logic to evaluate merge and interleave of a pair of arrays to the class array_live_range. - document class - update commit message Thanks Nicolai Hähnle for the pointers given. Signed-off-by: Gert Wollny <[email protected]> Acked-by: Dave Airlie <[email protected]>
* mesa/st/glsl_to_tgsi:rename lifetime to register_live_rangeGert Wollny2018-08-116-83/+90
| | | | | | | | | | | On one hand "live range" is the term used in the literature, and on the other hand a distinction is needed from the array live ranges. v4: Fix indentions and white spaces Reviewed-by: Nicolai Hähnle <[email protected]> (v3) Signed-off-by: Gert Wollny <[email protected]> Acked-by: Dave Airlie <[email protected]>
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