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* freedreno/ir3: handle VTXID_BASE for indirect drawsRob Clark2017-12-191-2/+41
* freedreno/ir3: add ctx->mem_to_mem()Rob Clark2017-12-194-14/+49
* freedreno/a5xx: use vertex_id_zero_baseRob Clark2017-12-192-20/+1
* r600: clear compressed flags in image state on unbind.Dave Airlie2017-12-191-0/+2
* swr: Account for index_bias in offsetsGeorge Kyriazis2017-12-181-3/+3
* r600: only reported tgsi ir compute support on evergreen+Dave Airlie2017-12-181-1/+3
* radv: Advertise sync fd import and export.Bas Nieuwenhuizen2017-12-181-4/+15
* radv: Implement sync file import/export for fences & semaphores.Bas Nieuwenhuizen2017-12-181-28/+87
* radv/amdgpu: wrap sync fd import/export.Bas Nieuwenhuizen2017-12-182-0/+26
* ac/nir: fix lds store for patch outputs.Dave Airlie2017-12-191-1/+1
* nir/linking: always set the used_across_stages/outputs_read bitsDave Airlie2017-12-191-6/+7
* spirv: Relax the validation conditions of OpSelectJason Ekstrand2017-12-181-4/+21
* radv: remove useless radv_cmask_info::base_address_regSamuel Pitoiset2017-12-181-1/+0
* amd/common: add ac_vgt_gs_mode() helperSamuel Pitoiset2017-12-184-55/+42
* amd/common: add ac_get_cb_shader_mask() helperSamuel Pitoiset2017-12-184-66/+40
* Revert "radv: do not load unused gl_LocalInvocationID/gl_WorkGroupID components"Samuel Pitoiset2017-12-181-5/+2
* radv: port merge tess info from anvDave Airlie2017-12-181-0/+40
* radv: Add external fence support.Bas Nieuwenhuizen2017-12-182-0/+22
* radv: Implement VK_KHR_external_fence_fd.Bas Nieuwenhuizen2017-12-182-0/+48
* radv: Implement fences based on syncobjs.Bas Nieuwenhuizen2017-12-183-15/+109
* amd/common: Add detection of the syncobj wait/signal/reset ioctls.Bas Nieuwenhuizen2017-12-182-0/+2
* radv: Add syncobj signal/reset/wait to winsys.Bas Nieuwenhuizen2017-12-182-0/+44
* configure/meson: Bump libdrm_amdgpu version requirement.Bas Nieuwenhuizen2017-12-182-2/+2
* android: fix vulkan driver buildTapani Pälli2017-12-181-2/+3
* android: fix undefined references to futex APITapani Pälli2017-12-181-0/+1
* docs: mark GL4.3 as finished for r600Dave Airlie2017-12-182-23/+24
* r600: export robust buffer accessDave Airlie2017-12-182-2/+2
* r600: export GLSL 430Dave Airlie2017-12-181-1/+1
* r600/cs: add compute support to capsDave Airlie2017-12-181-2/+2
* r600: always flush between gfx and computeDave Airlie2017-12-185-0/+21
* r600: fix unused variable warningDave Airlie2017-12-181-1/+0
* radv: Fix multi-layer blits.Bas Nieuwenhuizen2017-12-181-25/+24
* freedreno/a5xx: add a5xx blitterRob Clark2017-12-178-1/+498
* freedreno: add generic blitterRob Clark2017-12-177-2/+161
* freedreno: add non-draw batches for compute/blitRob Clark2017-12-1712-32/+82
* freedreno: track staging and shadow perf ctrs for the HUDRob Clark2017-12-175-0/+16
* freedreno: staging upload transfersRob Clark2017-12-173-43/+135
* freedreno: update generated headersRob Clark2017-12-177-63/+334
* anv: Remove unused variable.Bas Nieuwenhuizen2017-12-171-2/+0
* radeonsi: don't call force_dcc_off for buffersMarek Olšák2017-12-161-1/+1
* isl: Don't require VALIGN_2 for R32G32B32_FLOAT on Haswell.Kenneth Graunke2017-12-151-1/+3
* radeon/uvd: add and manage render picture listBoyuan Zhang2017-12-151-4/+25
* radeon/vcn: add and manage render picture listBoyuan Zhang2017-12-151-4/+24
* vl: remove is idr flagBoyuan Zhang2017-12-151-1/+0
* st/va: directly use idr pic flagBoyuan Zhang2017-12-151-5/+3
* radeon/vce: determine idr by pic typeBoyuan Zhang2017-12-151-1/+1
* radeon/vcn: determine idr by pic typeBoyuan Zhang2017-12-151-1/+1
* util: scons: wire up the sha1 testEmil Velikov2017-12-151-0/+7
* swr/rast: Move more RTAI handling out of binnerTim Rowley2017-12-152-12/+2
* swr/rast: EXTRACT2 changed from vextract/vinsert to vshuffleTim Rowley2017-12-153-61/+32
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