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* vc4: Add copy propagation between temps.Eric Anholt2014-08-084-0/+81
| | | | | | | | We put in a bunch of extra MOVs for program outputs, and this can clean those up. We should do uniforms, too, though. v2: Fix missing flagging of progress when we actually optimize. Caught by Aaron Watry.
* vc4: Add dead code elimination.Eric Anholt2014-08-084-3/+94
| | | | | | This cleans up a bunch of noise in the compiled coordinate shaders (since we don't need the varying outputs), and also from writemasked instructions with negated src operands.
* vc4: Add an initial pass of algebraic optimization.Eric Anholt2014-08-085-4/+125
| | | | | There was a lot of extra noise in my piglit shader dumps because of silly CMPs.
* vc4: Add support for CMP.Eric Anholt2014-08-084-1/+48
| | | | | | | | This took a couple of tries, and this is the squash of those attempts. v2: Fix register file conflicts on the args in the destination-is-accumulator case. v3: Rebase on helper change and qir_inst4 change.
* vc4: Make scheduling of NOPs a separate step from QIR -> QPU translation.Eric Anholt2014-08-083-90/+212
| | | | | This should also be used as a way to pair QIR instructions into QPU instructions later.
* vc4: Add WIP support for varyings.Eric Anholt2014-08-086-8/+59
| | | | | | It doesn't do all the interpolation yet, but more tests can run now. v2: Rebase on helpers.
* vc4: Use r3 instead of r5 for temps, since r5 only has 32 bits of storageEric Anholt2014-08-081-8/+8
| | | | | Reserving a whole accumulator for temps is awful in the first place, but I'll fix that later.
* vc4: Fix emit of ABSEric Anholt2014-08-081-1/+11
| | | | v2: Rebase on qir helpers.
* vc4: Add shader variant caching to handle FS output swizzle.Eric Anholt2014-08-083-65/+232
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* vc4: Load the tile buffer before incrementally drawing.Eric Anholt2014-08-082-27/+50
| | | | | | | We will want to occasionally disable this again when we do clear support. v2: Squash with the previous commit (I accidentally committed at two stages of writing the change)
* vc4: Don't reallocate the tile alloc/state bos every frame.Eric Anholt2014-08-082-10/+21
| | | | | This was a problem for the simulator since we don't free memory back to it, and it would soon just run out.
* vc4: Add VC4_DEBUG env optionEric Anholt2014-08-085-14/+63
| | | | | v2: Fix an accidental deletion of some characters from the copyright message (caught by Ilia Mirkin)
* vc4: Add support for SNE/SEQ/SGE/SLT.Eric Anholt2014-08-086-11/+96
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* vc4: Use the user's actual first vertex attribute.Eric Anholt2014-08-084-35/+70
| | | | | This is hardcoded to read it as RGBA32F so far, but starts to get more tests working.
* vc4: Fix UBO allocation when no uniforms are used.Eric Anholt2014-08-081-1/+2
| | | | We do rely on a real BO getting allocated, so make sure we ask for a non-zero size.
* vc4: Add initial support for math opcodesEric Anholt2014-08-082-1/+41
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* vc4: Switch to actually generating vertex and fragment shader code from TGSI.Eric Anholt2014-08-0812-247/+1243
| | | | | | | | | | | | | | | | | | This introduces an IR (QIR, for QPU IR) to do optimization on. It's a scalar, SSA IR in general. It looks like optimization is pretty easy this way, though I haven't figured out if it's going to be good for our weird register allocation or not (or if I want to reduce to basically QPU instructions first), and I've got some problems with it having some multi-QPU-instruction opcodes (SEQ and CMP, for example) which I probably want to break down. Of course, this commit mostly doesn't work, since many other things are still hardwired, like the VBO data. v2: Rewrite to use a bunch of helpers (qir_OPCODE) for emitting QIR instructions into temporary values, and make qir_inst4 take the 4 args separately instead of an array (all later callers wanted individual args).
* vc4: Start converting the driver to use vertex shaders.Eric Anholt2014-08-083-45/+177
| | | | | | | | Note: This is the cutoff point where I switched from developing primarily on the Pi to developing o the simulator. As a result, from this point on the code is untested on the Pi (the kernel code I have currently wasn't rendering anything at this commit, though the simulator renders successfully, suggesting kernel bugs).
* vc4: Initial skeleton driver import.Eric Anholt2014-08-0834-1/+4628
| | | | | | | | | | | | | | | | | | | This mostly just takes every draw call and turns it into a sequence of commands that clear the FBO and draw a single shaded triangle to it, regardless of the actual input vertices or shaders. I copied the initial driver skeleton mostly from freedreno, and I've preserved Rob Clark's copyright for those. I also based my initial hardcoded shaders and command lists on Scott Mansell (phire)'s "hackdriver" project, though the bit patterns of the shaders emitted end up being different. v2: Rebase on gallium megadrivers changes. v3: Rebase on PIPE_SHADER_CAP_MAX_CONSTS change. v4: Rely on simpenrose actually being installed when building for simulation. v5: Add more header duplicate-include guards. v6: Apply Emil's review (protection against vc4 sim and ilo at the same time, and dropping the dricommon drm bits) and fix a copyright header (thanks, Roland)
* draw: (trivial) use information about gs being present from variant keyRoland Scheidegger2014-08-091-5/+4
| | | | | | This is a purely cosmetic change. Reviewed-by: Brian Paul <[email protected]>
* draw: don't use clipvertex output if user plane clipping is disabledRoland Scheidegger2014-08-091-2/+2
| | | | | | | | | | The non-llvm path made sure that both clip and pre_clip_pos point to the data output by position, not clipvertex, if user based clipping is disabled. However, the llvm path did not, which apparently led to failures if gl_ClipVertex was written but user plane clipping not enabled (bug 80183). Why I have no idea really, but just make it match the non-llvm behavior... Reviewed-by: Brian Paul <[email protected]>
* i965: Get rid of backend_instruction::samplerChris Forbes2014-08-097-11/+0
| | | | | | | | The generators no longer use this. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/vec4/Gen8: Use src1 for sampler_index instead of ->sampler fieldChris Forbes2014-08-092-7/+15
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/vec4/Gen4-7: Use src1 for sampler_index instead of ->sampler fieldChris Forbes2014-08-092-8/+15
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/vec4: Pass sampler index in src1 for texture opsChris Forbes2014-08-092-7/+11
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/vec4: Collect all emits of texture ops into one placeChris Forbes2014-08-091-26/+12
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs/Gen8: Pass sampler_index to generate_texChris Forbes2014-08-092-7/+14
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs/Gen4-7: Pass sampler_index to generate_texChris Forbes2014-08-092-7/+14
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/blorp: Put sampler index in src1 of texture opsChris Forbes2014-08-091-1/+2
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: pass sampler as src1 of texture opChris Forbes2014-08-093-23/+25
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Collect all emits of texture ops for Gen5/6 into one placeChris Forbes2014-08-091-13/+18
| | | | | | | | | Reduces duplication, and will do so even more when we change the sampler plumbing. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Collect all emits of texture ops for Gen4 into one placeChris Forbes2014-08-091-20/+11
| | | | | | | | | Reduces duplication, and will do so even more when we change the sampler plumbing. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* configure: check for dladdr via AC_CHECK_FUNC/AC_CHECK_LIBPali Rohár2014-08-081-4/+3
| | | | | | | | | | | | | Use both macros as in some cases using AC_CHECK_FUNCS alone may fail. Thus HAVE_DLADDR will not be defined, and as a result most of the code in megadriver_stub.c will not be compiled. Breaking the backwards compatibility between older libGL/xserver(s) and DRI megadrivers. Cc: Jon TURNEY <[email protected]> Cc: "10.2" <[email protected]> [Emil Velikov] Commit message. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* util: remove ralloc_testEmil Velikov2014-08-084-106/+5
| | | | | | | | | The tests in an empty stub, which we're currently building twice. If anyone is interested in expanding it (adding actual tests) they can always bring it back. Suggested-by: Kenneth Graunke <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* gallivm: Handle MSAA textures in emit_fetch_texelsDarius Goad2014-08-081-2/+7
| | | | | | | | | | | | This support is preliminary due to the fact that MSAA is not actually implemented. However, this patch does fix the piglit test: spec/!OpenGL 3.2/glsl-resource-not-bound 2DMS (bug #79740). (v2 RS: don't emit 4th coord as explicit lod) Reviewed-by: Roland Scheidegger <[email protected]>
* draw: hack around weird primitive id input in gsRoland Scheidegger2014-08-083-5/+21
| | | | | | | | | | | | | | | | | | | | | | The distinction between system values and ordinary inputs is not very obvious in gallium - further fueled by the fact that they use the same semantic names. Still, if there's any value which imho really is a system value, it's the primitive id input into the gs (while earlier (tessleation) stages could read it, it is _always_ generated by the system). For some odd reason though (which I'd classify as a bug but seems too complicated to fix) the glsl compiler in mesa treats this as an ordinary varying, and everything else after that (including the state tracker and other drivers) just go along with that. But input fetching in gs for llvm based draw was definitely limited to the ordinary (2-dimensional) inputs so only worked with other state trackers, the code was also additionally relying on tgsi_scan_shader filling uses_primid correctly which did not happen neither (would set it only for all stages if it was a system value, but only set it for the fragment shader if it was an input value). This fixes piglit glsl-1.50-geometry-primitive-id-restart and primitive-id-in in llvmpipe. Reviewed-by: Brian Paul <[email protected]>
* draw: fix prim id float cast for non-llvm pathRoland Scheidegger2014-08-081-8/+4
| | | | | | | These values are always uints, casting them to floats does no good. Fixes piglit glsl-1.50-geometry-primitive-id-restart tests for softpipe. Reviewed-by: Brian Paul <[email protected]>
* clover: Add support for CL_MAP_WRITE_INVALIDATE_REGIONBruno Jiménez2014-08-082-0/+14
| | | | | | | | | | | | | | | | OpenCL 1.2 CL_MAP_WRITE_INVALIDATE_REGION sounds a lot like PIPE_TRANSFER_DISCARD_RANGE: From OpenCL 1.2 spec: The contents of the region being mapped are to be discarded. From p_defines.h: Discards the memory within the mapped region. v2: Move the code for validating flags to the front-end as suggested by Francisco Jerez Reviewed-by: Francisco Jerez <[email protected]>
* ilo: break down the format tableChia-I Wu2014-08-081-299/+431
| | | | | | | The PRMs no longer have a single table for format capabilities. Multiple tables take up less space, and are easier to maintain. Encode typed write information while at it.
* i965: Emit a performance warning on conditional rendering.Kenneth Graunke2014-08-081-0/+5
| | | | | | | | | We have a CPU-side implementation of conditional rendering; it really should be done on the GPU. It's not necessarily that hard, but nobody has gotten to fixing it yet. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Set ExecSize to 16 for loop instructions in SIMD16 shaders.Kenneth Graunke2014-08-081-5/+8
| | | | | | | | | | | | | | | | | | | Previously, we explicitly set the execution size to BRW_EXECUTE_8 and disabled compression for loop instructions. I can't imagine how this could be correct in SIMD16 mode. Looking at the history, it appears that this code has used BRW_EXECUTE_8 since 2007, when we had a SIMD8 backend that supported control flow and a separate SIMD16 backend that didn't. Presumably, when we added SIMD16 support for shaders with control flow, we simply neglected to update it. Note that Gen4-5 don't support SIMD16 on shaders with control flow. This might be a candidate for stable, but would need to be rewritten completely due to the brw_inst API changes in master. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/eu: Merge brw_CONT and gen6_CONT.Kenneth Graunke2014-08-084-28/+7
| | | | | | | The only difference is setting PopCount on Gen4-5. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/eu: Drop redundant brw_set_src0/brw_set_dest from gen6_CONT.Kenneth Graunke2014-08-081-2/+0
| | | | | | | We shouldn't need to set them, then set them differently. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* util: add src/util/format_srgb.c to .gitignoreJuha-Pekka Heikkila2014-08-081-0/+1
| | | | | | | | | format_srgb.c is generated by format_srgb.py python script, having format_srgb.c in git ignore list will silence git complaints about untracked file. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: Fold _mesa_uniform_merge_location_offset into its only callerIan Romanick2014-08-073-48/+3
| | | | | | | | Also delete the comment before that function. Everything in that comment was either stale, wrong, or captured elsewhere. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Fold _mesa_uniform_split_location_offset into its only callerIan Romanick2014-08-072-22/+6
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl_to_tgsi: Delete unused function set_uniform_initializerIan Romanick2014-08-071-72/+0
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Use MAX2 to calculate maximum uniform elementIan Romanick2014-08-071-3/+1
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Have validate_uniform_parameters return the gl_uniform_storage pointerIan Romanick2014-08-071-31/+30
| | | | | | | | This simplifies all the callers, and it enables the removal of one of the function parameters. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl/glcpp: Rename one test to avoid a duplicate test numberCarl Worth2014-08-072-0/+0
| | | | | | | | | | | With two tests both numbered 118, there was a confusing off-by-two difference between the last test number and the total number of tests (as reported by glcpp-test). With this rename, there's only an off-by-one difference left, (which is easy to understand given the zero-based test numbering). Reviewed-by: Ian Romanick <[email protected]>
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