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* dri3: Wait for all pending swapbuffers to be scheduled before touching the frontThomas Hellstrom2017-08-032-0/+21
| | | | | | | | | | | | | This implements a wait for glXWaitGL, glXCopySubBuffer, dri flush_front and creation of fake front until all pending SwapBuffers have been committed to hardware. Among other things this fixes piglit glx-copy-sub-buffers on dri3. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: <[email protected]> (cherry picked from commit 185ef06fd2db782d9d3d6046580f7cece02c4797)
* gallium/radeon: fix ARB_query_buffer_object conversion to booleanNicolai Hähnle2017-08-031-1/+2
| | | | | | | | | | The issue here is that the immediate is treated as a 64-bit value, and fetching it does not work reliably with swizzles that are different from xy and zw. Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit da83687c4ba7e9022f6f14176393a9e3c6391ed5)
* fixup! cherry-ignore: add a bunch more commits to the listEmil Velikov2017-08-031-1/+0
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* nir: fix algebraic optimizationsConnor Abbott2017-08-031-2/+2
| | | | | | | | | The optimizations are only valid for 32-bit integers. They were mistakenly firing for 64-bit integers as well. Cc: [email protected] Reviewed-by: Matt Turner <[email protected]> (cherry picked from commit de914615753678c5514733a37ac7d0360a43e525)
* cherry-ignore: add a bunch more commits to the listEmil Velikov2017-08-031-0/+15
| | | | Signed-off-by: Emil Velikov <[email protected]>
* etnaviv: fix memory leak when BO allocation failsLucas Stach2017-08-031-1/+5
| | | | | | | | | | | The resource struct is already allocated at this point and should be freed properly. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Philipp Zabel <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]> (cherry picked from commit 4fb9f97047eb1e43c47cb7cacba27ccd20383eff)
* st/dri: Check get-handle return value in queryImageDaniel Stone2017-08-031-6/+9
| | | | | | | | | | | | | | In the DRIImage queryImage hook, check if resource_get_handle() failed and return FALSE if so. Signed-off-by: Daniel Stone <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit b4a18f13ce7f0e7d0307fb3388819345616752ce) [Emil Velikov: drop offset and modifier hunks - not in branch] Signed-off-by: Emil Velikov <[email protected]> Conflicts: src/gallium/state_trackers/dri/dri2.c
* radv: for stencil only set Z tile mode index to same valueDave Airlie2017-08-031-0/+2
| | | | | | | | | | | | | | | | | | On SI this was causing a hang in dEQP-VK.pipeline.render_to_image.core.2d_array.mipmap.r16g16_sint_s8_uint This was due to not handling the tile mode index for depth like I fixed previously for new GPUs. Fixes: 01d0c5a9 (radv: fix stencil regression since new addrlib import) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 800d1622096ca52b955bdfc20eb770b80ef15221) [Emil Velikov: XXX] Signed-off-by: Emil Velikov <[email protected]> Conflicts: src/amd/vulkan/radv_device.c
* radv/ac: port SI TC L1 write corruption fix.Dave Airlie2017-08-031-3/+5
| | | | | | | | | | This ports 72e46c988 to radv. radeonsi: apply a TC L1 write corruption workaround for SI Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit e77ff11ffe1a52b8e17a847f263746c849db3f11)
* radv/ac: realign SI workaround with radeonsi.Dave Airlie2017-08-031-2/+3
| | | | | | | | | | | | | This ports: da7453666ae radeonsi: don't apply the Z export bug workaround to Hainan to radv. Just noticed in passing. Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit a81e99f50a718790de379087c9f5a636e32b2a28)
* radv: fix buffer views on SI/CIK.Dave Airlie2017-08-031-0/+5
| | | | | | | | | | Fixes CTS dEQP-VK.memory.pipeline_barrier.host_write_uniform_texel_buffer.1024 on SI/CIK with radv. Fixes: f4e499ec (radv: add initial non-conformant radv vulkan driver) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit ca82ef5ac75e50abb109986b55002cca24f7c0fb)
* radv: fix non-0 based layer clears.Dave Airlie2017-08-031-4/+9
| | | | | | | | | | | | If the layer base was > 0, it wasn't getting passed as the start instance or getting added in the shaders. Fixes CTS dEQP-VK.api.image_clearing.core.clear_color_attachment.2d_r8_uint_multiple_layers Fixes: 7e0382fb (radv: add support for layered clears (v2)) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 75392e76adf143070a5f208febd8da31b39b7676)
* swr: remove unneeded fallback strcasecmp defineEmil Velikov2017-08-031-5/+0
| | | | | | | | | | The last user of the function was removed with earlier commit. Fixes: 50842e8a931 ("swr: replace gallium->swr format enum conversion") Cc: Tim Rowley <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Tim Rowley <[email protected]> (cherry picked from commit a0755f2e6a1b41b2c5e295fa5ff8eb8dfbf5eb41)
* i965: use strtol to convert the integer deviceID overrideEmil Velikov2017-08-031-1/+1
| | | | | | | | | | | | | | | | | One can override the deviceID, by setting the INTEL_DEVID_OVERRIDE variable. A few symbolic names or a numerical value for the actual device ID is accepted. At the same time we're using strtod (string to double) to convert the string to a decimal numeral. A seeming thinko, made by the original commit that introduces the code in libdrm_intel and got here with the import. Fixes: 514db96c117a ("i965: Import libdrm_intel.") Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit 647b5a18df6e423e1a15d92bc767ba0cf04493a3)
* anv/pipeline: do not use BITFIELD64_BIT()Juan A. Suarez Romero2017-08-031-1/+1
| | | | | | | | | | In the previous commit, forgot to apply v2 suggestions. Fixes: 28d0c38 (anv/pipeline: use unsigned long long constant to check enable vertex inputs) Signed-off-by: Juan A. Suarez Romero <[email protected]> (cherry picked from commit 5cd4ece34ebdc1383f1e2376c88097d06544e2f6)
* travis: lower SWR requirement to GCC 4.8, aka std=c++11Emil Velikov2017-08-031-8/+4
| | | | | | | | | | With ealier commit we relaxed the requirement from C++14 to C++11. Update the build script so that it Cc: Tim Rowley <[email protected] Fixes: 0b80b025021 ("swr: relax c++ requirement from c++14 to c++11") Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 459274144dbd9227a57858316b996cede9094bca)
* i965: Resolve framebuffers before signaling the fenceChris Wilson2017-08-031-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From KHR_fence_sync: When the condition of the sync object is satisfied by the fence command, the sync is signaled by the associated client API context, causing any eglClientWaitSyncKHR commands (see below) blocking on <sync> to unblock. The only condition currently supported is EGL_SYNC_PRIOR_COMMANDS_COMPLETE_KHR, which is satisfied by completion of the fence command corresponding to the sync object, and all preceding commands in the associated client API context's command stream. The sync object will not be signaled until all effects from these commands on the client API's internal and framebuffer state are fully realized. No other state is affected by execution of the fence command. If clients are passing the fence fd (from EGL_ANDROID_native_fence_sync) to a compositor, that fence must only be signaled once the framebuffer is resolved and not before as is currently the case. v2: fixup assert to use GL_SYNC_GPU_COMMANDS_COMPLETE (Chad) Reported-by: Sergi Granell <[email protected]> Fixes: c636284ee8ee ("i965/sync: Implement DRI2_Fence extension") Signed-off-by: Chris Wilson <[email protected]> Cc: Sergi Granell <[email protected]> Cc: Rob Clark <[email protected]> Cc: Chad Versace <[email protected]> Cc: Daniel Stone <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]> (cherry picked from commit 618be8cc1ad1760103930b69ffbf528d7b861ab3)
* bin/cherry-ignore: add radeonsi "fix of a fix"Emil Velikov2017-08-031-0/+4
| | | | | | The commit addresses an earlier fix, which did not land in branch. Signed-off-by: Emil Velikov <[email protected]>
* cherry-ignore: add yet another bindless textures fixEmil Velikov2017-08-031-0/+3
| | | | Signed-off-by: Emil Velikov <[email protected]>
* cherry-ignore: add "st/glsl_to_tgsi: fix getting the image type for array of ↵Emil Velikov2017-08-031-0/+3
| | | | | | | | structs" Addresses commit which did not land in branch. Signed-off-by: Emil Velikov <[email protected]>
* cherry-ignore: add bindless textures fixEmil Velikov2017-08-031-0/+3
| | | | | | The bindless work did not land in branch. Signed-off-by: Emil Velikov <[email protected]>
* cherry-ignore: ignore reverted st/mesa commitEmil Velikov2017-08-031-0/+3
| | | | | | Applied to master and reverted shortly afterwords. Signed-off-by: Emil Velikov <[email protected]>
* cherry-ignore: add a couple of radeonsi/gfx9 commitsEmil Velikov2017-08-031-0/+4
| | | | | | | They depend on the merged shaders (re)work which landed past the 17.1 branchpoint. Signed-off-by: Emil Velikov <[email protected]>
* cherry-ignore: add "swr: fix transform feedback logic"Emil Velikov2017-08-031-0/+4
| | | | | | | Explicit 17.2 nomination, since it depends on refactoring past the 17.1 branchpoint. Signed-off-by: Emil Velikov <[email protected]>
* cherry-ignore: add "swr/rast: non-regex knob fallback code for gcc < 4.9"Emil Velikov2017-08-031-0/+4
| | | | | | Addresses commit merged past the 17.1 brancpoint. Signed-off-by: Emil Velikov <[email protected]>
* cherry-ignore: add a couple of radeon commitsEmil Velikov2017-08-031-0/+6
| | | | | | | Both are explicit 17.2 nominations, since they depend on work which landed past the 17.1 branchpoint. Signed-off-by: Emil Velikov <[email protected]>
* gallium/radeon: make S_FIXED function signed and move it to shared codeMarek Olšák2017-08-033-9/+5
| | | | | | | | | | | | This fixes a bug uncovered by: 2412c4c81ea0488df865817a0de91ec46e359b72 util: Make CLAMP turn NaN into MIN. Cc: 17.2 <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> (cherry picked from commit 433f6f7ac9ed6624fec02cc055c3bfa247dba185)
* radeonsi/gfx9: reduce max threads per block to 1024 on gfx9+Nicolai Hähnle2017-08-031-15/+27
| | | | | | | | | | | | | | | The number of supported waves per thread group has been reduced to 16 with gfx9. Trying to use 32 waves causes hangs, and barriers might not work correctly with > 16 waves. Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit a0e6b9a2db5aa5f06a4f60d270aca8344e7d8b3f) [Emil Velikov: add a HAVE_LLVM check, as applicable in branch] Signed-off-by: Emil Velikov <[email protected]> Conflicts: src/gallium/drivers/radeon/r600_pipe_common.c
* radeonsi: fix detection of DRAW_INDIRECT_MULTI on SINicolai Hähnle2017-08-031-2/+2
| | | | | | | | | | | | | | | | | The firmware version numbers for SI were wrong. The new numbers are probably too conservative (we don't have a definitive answer by the firmware team), but DRAW_INDIRECT_MULTI has been confirmed to work with these versions on Tahiti (by Gustaw) and on Verde (by myself). While this is technically adding a feature, it's a feature we thought we had for a long time. The change is small enough and we're early enough in the 17.2 release cycle that it should still go in. Reported-by: Gustaw Smolarczyk <[email protected]> Cc: 17.2 <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 65fbaab0b74b6b5a2ac483d48beeefa0a29ff15e)
* anv: only expose up to 28 vertex attributesIago Toral Quiroga2017-08-031-1/+1
| | | | | | | | | | | | | The EU limit of 128 GRFs should allow 32 vertex elements of 4 GRFs. However, the maximum allowed value of "Vertex URB Entry Read Length" in SIMD8 is 15. And 15 * 8 = 120 gives us a limit of 30 vertex elements. Because we also need to reserve a vertex buffer to upload VertexIndex/InstanceIndex and another to upload DrawID when needed, we can only expose 28. Cc: "17.2" <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit 31f1863ace73d31a579e5c36252a957818ad09cf)
* anv/cmd_buffer: fix off by one error in assertionIago Toral Quiroga2017-08-031-1/+1
| | | | | | Cc: "17.2" <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit a848e693efc8e2a1d355dc1076409968b374153f)
* cherry-ignore: add "i965: Fix = vs == in MCS aux usage assert."Emil Velikov2017-08-031-0/+3
| | | | | | Addesses 0f9b609cf4f, which landed shortly before the 17.2 branchpoint. Signed-off-by: Emil Velikov <[email protected]>
* cherry-ignore: add "i965: Fix offset addition in get_isl_surf"Emil Velikov2017-08-031-0/+3
| | | | | | Addesses 63a43f41619, which landed shortly before the 17.2 branchpoint. Signed-off-by: Emil Velikov <[email protected]>
* i965: perf: flush batchbuffers at the beginning of queriesLionel Landwerlin2017-08-031-0/+8
| | | | | | | | | | | | | | | | | | | | | | As Chris commented, it makes more sense to have batch buffer flushes before the query. Usually applications like frame_retrace do a series of queries and in that case, with flushes at the end of the queries, we might still have the first query contained in 2 different batchs. More generally it would be quite usual to have the query contained in 2 batch buffers because we never now what's the fill rate of the current batch buffer. If we move the flushing at the beginning of the queries, it's pretty much guaranteed that queries will be contained in a single batch buffer (unless the amount of commands is huge, but then it's only fair to include reloading request times in the measurements). Fixes: adafe4b733c02 ("i965: perf: minimize the chances to spread queries across batchbuffers") Reported-by: Chris Wilson <[email protected]> Signed-off-by: Lionel Landwerlin <[email protected]> Cc: "17.2 17.1" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit 9f439ae1201cb049ffedb9b0e2d4f393fb0a761e)
* broadcom/vc4: Prefer blit via rendering to the software fallback.Eric Anholt2017-08-031-6/+8
| | | | | | | | I don't know how I managed to leave this here for so long. Found when working on a 1:1 overlapping blit extension for X11. Cc: [email protected] (cherry picked from commit 93fec49a75ce799bb6fe167f9409fd553a5781c6)
* etnaviv: Clear lbl_usage array correctlyWladimir J. van der Laan2017-08-031-1/+1
| | | | | | | | | | | | | | Fill the entire array instead of just a quarter. This avoids crashes with large shaders. (currently this never causes a problem because shaders larger than 2048/4 instructions are not supported by this driver on any hardware, but it will cause problems in the future) Fixes: ec436051899 ("etnaviv: fix shader miscompilation with more than 16 labels") Cc: [email protected] Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> (cherry picked from commit 15a1ceb127b70ac98b03cae051927f75fb7ee204)
* swr: don't forget to link AVX/AVX2 against pthreadsEmil Velikov2017-08-031-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | Seems like the backends have been using pthreads since day one, yet we've been missing the link. With later commit we'll fix a typo, hence the libraries will be build with -Wl,no-undefined, aka failing the build on unresolved symbols. v2: Split from a larger patch. Cc: [email protected] Cc: Bruce Cherniak <[email protected]> Cc: Tim Rowley <[email protected]> Cc: Laurent Carlier <[email protected]> Fixes: c6e67f5a9373e916a8d2 "gallium/swr: add OpenSWR rasterizer" Reviewed-by: Eric Engestrom <[email protected]> Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 33d397ada50a1d1f485205e847003dc48146ec19) [Emil Velikov: add PTHREAD_LIBS to COMMON_LIBADD] Signed-off-by: Emil Velikov <[email protected]> Conflicts: src/gallium/drivers/swr/Makefile.am
* cherry-ignore: add "anv: Transition MCS buffers from the undefined layout"Emil Velikov2017-08-031-0/+4
| | | | | | Depends on earlier refactoring commit 6235f08ff8870636d89d2181e0a9dfc3ebec7b45 Signed-off-by: Emil Velikov <[email protected]>
* swr/rast: quit using linux-specific gettid()Tim Rowley2017-08-032-4/+3
| | | | | | | | | | | | | | Linux-specific gettid() syscall shouldn't be used in portable code. Fix does assume a 1:1 thread:LWP architecture, but works for our current target platforms and can be revisited later if needed. Fixes unresolved symbol in linux scons builds. v2: add comment in code about the 1:1 assumption. Cc: [email protected] Reviewed-by: Bruce Cherniak <[email protected]> (cherry picked from commit d1e7153228304eb1be85580cbfdea1a57c5f203b)
* gallium/util: fix nondeterministic avx512 detectionTim Rowley2017-08-031-1/+1
| | | | | | | | | | | cpuid.7 requires cx=0 to select the extended feature leaf. avx512 detection was using the non-indexed cpuid resulting in random non-detection of avx512. Cc: [email protected] Reviewed-by: Roland Scheidegger <[email protected]> (cherry picked from commit 131b9f644cbe70728ba02878483e22459400bcb4)
* anv/image: Fix VK_IMAGE_CREATE_CUBE_COMPATIBLE_BITChad Versace2017-08-031-3/+4
| | | | | | | | | | | | We incorrectly detected VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT. We looked for the bit in VkImageCreateInfo::usage, but it's actually in VkImageCreateInfo::flags. Found by assertion failures while enabling VK_ANDROID_native_buffer. Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit 5d6905211355464de4885492511e5f9d936cc058)
* swrast: add dri2ConfigQueryExtension to the correct extension listEmil Velikov2017-08-031-1/+1
| | | | | | | | | | | | | | | The extension should be in the list as returned by getExtensions(). Seems to have gone unnoticed since close to nobody wants to change the vblank mode for the software driver. v2: Rebase Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]> (v1) (cherry picked from commit 7791949dadd5af707055d0076874177e5e8e2133) [Emil Velikov: drop st/dri hunk, squash correct swrast piece] Signed-off-by: Emil Velikov <[email protected]>
* nir: Use nir_src_copy instead of direct assignments.Kenneth Graunke2017-08-032-3/+3
| | | | | | | | | | | | | | | | | | | | | If the source is an indirect register, there is ralloc'd data. Copying with a direct assignment will copy the pointer, but the data will still belong to the old instruction's memory context. Since we're lowering and throwing away instructions, that could free the data by mistake. Instead, use nir_src_copy, which properly handles this. This is admittedly not a common case, so I think the bug is real, but unlikely to be hit. Cc: [email protected] Reviewed-by: Matt Turner <[email protected]> (cherry picked from commit 0320bb2c6cb27370e2389b392b63f8d05c7cb4c7) [Emil Velikov: drop nir_lower_atomics_to_ssbo.c - not in branch] Signed-off-by: Emil Velikov <[email protected]> Conflicts: src/compiler/nir/nir_lower_atomics_to_ssbo.c
* nir: fix nir_opt_copy_prop_vars() for arrays of arraysTimothy Arceri2017-08-031-6/+6
| | | | | | | | | | | Previously we only incremented the guide for a single dimension/wildcard. V2: rework logic to avoid code duplication Reviewed-by: Jason Ekstrand <[email protected]> Cc: [email protected] (cherry picked from commit 3f0fb23b039443d581d221b1fe9158f9cc81ccd6)
* nir/vars_to_ssa: Handle missing struct members in foreach_deref_nodeJason Ekstrand2017-08-031-2/+6
| | | | | | | | | | This can happen if, for instance, you have an array of structs and there are both direct and wildcard references to the same struct and some members only have direct or only have indirect. Reviewed-by: Timothy Arceri <[email protected]> Cc: [email protected] (cherry picked from commit ecf91898e0a8e144adb82d72aecf1224e77ee31b)
* anv/image: Add INPUT_ATTACHMENT to the list of required usagesJason Ekstrand2017-08-031-0/+1
| | | | | | | | | | | | | | | | From the Vulkan 1.0.53 spec VU for vkCreateImageView: "image must have been created with a usage value containing at least one of VK_IMAGE_USAGE_SAMPLED_BIT, VK_IMAGE_USAGE_STORAGE_BIT, VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT, VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT, or VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT" We were missing VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT from out list. Reviewed-by: Lionel Landwerlin <[email protected]> Cc: [email protected] (cherry picked from commit c5700ed72e765043bb1c8523a05ade235496e053)
* anv: Stop leaking the no_aux sampler surface stateJason Ekstrand2017-08-031-0/+5
| | | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Cc: [email protected] (cherry picked from commit cbdfd1daa24ee9a7a612f7b0e9aa4610af05e211)
* anv/cmd_buffer: Properly handle render passes with 0 attachmentsJason Ekstrand2017-08-031-12/+11
| | | | | | | | | We were early returning and never created the NULL surface state. Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: James Legg <[email protected]> Cc: [email protected] (cherry picked from commit bd41564746ca4f4bd46185b99754eaa012c359e5)
* st/va: Fix scaling list ordering for H.265Mark Thompson2017-08-033-7/+49
| | | | | | | | | | | | | | Mesa here requires the scaling lists in diagonal scan order, but VAAPI passes them in raster scan order. Therefore, rearrange the elements when copying. v2: Move scan tables to vl_zscan.c. Fix type in size assertion. Cc: [email protected] Signed-off-by: Mark Thompson <[email protected]> Reviewed-by: Christian König <[email protected]> (cherry picked from commit 63dcfed81f011dae5ca68af3369433be28135415)
* radv: advertise v6 of the wayland surface extensionEmil Velikov2017-08-031-1/+1
| | | | | | | | | | | | | | Jason updated the Khronos spec to explicitly state that Wayland surfaces must support VK_PRESENT_MODE_MAILBOX_KHR. ANV did so since day one (back in 2015) Cc: [email protected] Cc: Bas Nieuwenhuizen <[email protected]> Cc: Dave Airlie <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit 4168c162c5bcbbfc6c712466b9c3d7d0dbac06e5)
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