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* pan/midgard: Implement OP_IS_STORE with tableAlyssa Rosenzweig2019-10-202-13/+2
* pan/midgard: Tableize load/store opsAlyssa Rosenzweig2019-10-205-70/+102
* pan/midgard: Factor out mir_get_alu_srcAlyssa Rosenzweig2019-10-201-6/+8
* pan/midgard/disasm: Fix printing 8-bit/16-bit masksAlyssa Rosenzweig2019-10-201-49/+30
* pan/midgard: Identify 64-bit atomic opcodesAlyssa Rosenzweig2019-10-202-0/+20
* pan/midgard: Debug mir_insert_instruction_after_scheduledAlyssa Rosenzweig2019-10-201-2/+6
* etnaviv: keep track of buffer valid ranges for PIPE_BUFFERChristian Gmeiner2019-10-203-2/+35
* etnaviv: store updated usage in pipe_transfer objectChristian Gmeiner2019-10-201-8/+8
* etnaviv: fix code styleChristian Gmeiner2019-10-201-1/+2
* anv: fix memory leak on device destroyLionel Landwerlin2019-10-201-1/+11
* etnaviv: fix compile warningsChristian Gmeiner2019-10-203-7/+0
* mesa: Redefine the RG formats as array formats.Eric Anholt2019-10-2015-117/+67
* gallium: Drop the unused PIPE_FORMAT_A*L* formats.Eric Anholt2019-10-203-30/+0
* mesa: Replace MESA_FORMAT_L8A8/A8L8 UNORM/SNORM/SRGB with an array format.Eric Anholt2019-10-2020-103/+62
* mesa: Replace the LA16_UNORM packed formats with one array format.Eric Anholt2019-10-2010-22/+16
* radeon: Drop the unused first arg of OUT_BATCH_RELOC.Eric Anholt2019-10-209-24/+24
* radeon: Fill in the TXOFFSET field containing the tile bits in our relocs.Eric Anholt2019-10-202-4/+5
* r100/r200: factor out txformat/txfilter setup from the TFP path.Eric Anholt2019-10-202-22/+10
* lima: fix PP stack sizeVasily Khoruzhick2019-10-191-2/+1
* freedreno/a5xx: enable a510Marijn Suijten2019-10-191-0/+1
* Appveyor/Meson: Add build test of osmesa galliumProdea Alexandru-Liviu2019-10-191-1/+1
* anv: fix vkUpdateDescriptorSets with inline uniform blocksLionel Landwerlin2019-10-191-3/+3
* freedreno/ir3: handle imad24_ir3 case in UBO loweringRob Clark2019-10-181-2/+27
* freedreno/ir3: add imul24 opcodeRob Clark2019-10-181-0/+3
* freedreno/ir3: optimize immed 2nd src to madRob Clark2019-10-181-2/+11
* freedreno/ir3: add rule to generate imad24Rob Clark2019-10-181-0/+5
* nir: add nir_lower_amul passRob Clark2019-10-187-3/+335
* nir: add address calc related opt rulesRob Clark2019-10-181-0/+16
* nir: add amul instructionRob Clark2019-10-187-7/+38
* nir: Add a new ALU nir_op_imul24Rob Clark2019-10-181-0/+3
* freedreno/ir3: Handle newly added opcode nir_op_imad24_ir3Eduardo Lima Mitev2019-10-181-0/+3
* nir: Add a new ALU nir_op_imad24_ir3Eduardo Lima Mitev2019-10-181-0/+7
* freedreno/ir3: rename mul.s/mul.uRob Clark2019-10-185-12/+12
* nir/search: fix the PoT helpersRob Clark2019-10-182-4/+7
* freedreno/ir3: enable pre-fs texture fetch for a6xxRob Clark2019-10-181-0/+6
* turnip: add support for pre-fs texture fetchRob Clark2019-10-181-3/+21
* freedreno/a6xx: add support for pre-fs texture fetchRob Clark2019-10-181-5/+23
* freedreno/ir3: Add support for texture sampling pre-dispatchHyunjun Ko2019-10-181-2/+73
* freedreno/ir3: Add a NIR pass to select tex instructions eligible for pre-fetchEduardo Lima Mitev2019-10-183-0/+199
* freedreno/ir3: force i/j pixel to r0.xRob Clark2019-10-181-0/+22
* freedreno/ir3: add pre-dispatch tex fetch to disasmRob Clark2019-10-181-0/+10
* freedreno/ir3: add dummy bary.f(ei) for pre-fs-fetchRob Clark2019-10-181-0/+19
* freedreno/ir3: fixup register footprint to account for prefetchRob Clark2019-10-181-0/+14
* freedreno/ir3: add meta instruction for pre-fs texture fetchRob Clark2019-10-186-3/+33
* freedreno/ir3: don't DCE ij_pix if used for pre-fs-texture-fetchRob Clark2019-10-183-6/+14
* freedreno/ir3: track sysval slot for inputsRob Clark2019-10-183-0/+12
* freedreno/ir3: remove unused ir3_instruction::inoutRob Clark2019-10-183-5/+0
* freedreno/ir3: Add data structures to support texture pre-fetchHyunjun Ko2019-10-181-0/+37
* freedreno: update registersRob Clark2019-10-183-3/+24
* nir: Add new texop nir_texop_tex_prefetchEduardo Lima Mitev2019-10-183-0/+6
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