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* gallium/ttn: Convert inputs and outputs to derefs of variables.Eric Anholt2018-10-154-69/+64
| | | | | | | | | | | This means that TTN shaders more closely resemble GTN shaders: they have inputs and outputs as variable derefs, with the variables having their .driver_location already set up for you. This will be useful for v3d to do input variable DCE in NIR, which we can't do when the TTN shaders never have a pre-nir_lower_io stage. Acked-by: Rob Clark <[email protected]>
* gallium/ttn: Fix the type of gl_FragDepth.Eric Anholt2018-10-151-0/+1
| | | | | | | | In TGSI we have a vec4 of which only .z is used, but for NIR we should be using a float the same as other NIR IR. We were already moving TGSI's .z to the .x channel. Acked-by: Rob Clark <[email protected]>
* freedreno/a6xx: Enable blitterKristian H. Kristensen2018-10-155-0/+623
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a6xx: Update headersKristian H. Kristensen2018-10-151-16/+30
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a6xx: Remove unnecessary GRAS_2D_BLIT_INFO writeKristian H. Kristensen2018-10-151-2/+0
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* anv: Don't advertise ASTC support on BSWJason Ekstrand2018-10-151-0/+8
| | | | | Tested-by: Mark Janes <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* radv: do not force the flat qualifier for clip/cull distancesSamuel Pitoiset2018-10-151-2/+2
| | | | | | | | | | This fixes some new CTS that reads clip/cull distances from the fragment shader stage: dEQP-VK.clipping.user_defined.clip_* Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: bump discreteQueuePriorities to 2Samuel Pitoiset2018-10-151-1/+1
| | | | | | | | | It's the minimum value required by the spec. This fixes dEQP-VK.api.info.device.properties. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* anv: Split dispatch tables into device and instanceJason Ekstrand2018-10-153-91/+230
| | | | | | | | | | | | | | | | | | | | There's no reason why we need generate trampoline functions for instance functions or carry N copies of the instance dispatch table around for every hardware generation. Splitting the tables and being more conservative shaves about 34K off .text and about 4K off .data when built with clang. Before splitting dispatch tables: text data bss dec hex filename 3224305 286216 8960 3519481 35b3f9 _install/lib64/libvulkan_intel.so After splitting dispatch tables: text data bss dec hex filename 3190325 282232 8960 3481517 351fad _install/lib64/libvulkan_intel.so Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Drop assert about number of uniforms in ARB handling.Kenneth Graunke2018-10-151-3/+2
| | | | | | | | | | | My recent prog_to_nir patch started making new sampler uniforms, which apparently increased the number of parameters. We used to poke at the one parameter directly, making it important that there was only one, but we haven't done that in a while. It should be safe to just delete the assertion. Fixes: 1c0f92d8a8c "nir: Create sampler variables in prog_to_nir." Reviewed-by: Jason Ekstrand <[email protected]>
* vulkan: Add the fuchsia headersJason Ekstrand2018-10-152-0/+62
| | | | | | These were missing in the last couple of spec updates. Acked-by: Lionel Landwerlin <[email protected]>
* radv: Implement VK_EXT_pci_bus_info.Bas Nieuwenhuizen2018-10-153-0/+13
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/u_transfer_helper: Add support for separate Z24/S8 as well.Kenneth Graunke2018-10-145-22/+60
| | | | | | | | | | | | | | | | u_transfer_helper already had code to handle treating packed Z32_S8 as separate Z32_FLOAT and S8_UINT resources, since some drivers can't handle that interleaved format natively. Other hardware needs depth and stencil as separate resources for all formats. For example, V3D3 needs this for 24-bit depth as well. This patch adds a new flag to lower all depth/stencils formats, and implements support for Z24_UNORM_S8_UINT. (S8_UINT_Z24_UNORM is left as an exercise to the reader, preferably someone who has access to a machine that uses that format.) Reviewed-by: Eric Anholt <[email protected]>
* gallium/format: Add a helper to combine separate Z24 and S8 stencil.Kenneth Graunke2018-10-142-0/+22
| | | | | | | This new function takes separate Z24 depth and S8 stencil sources, and packs them into a single combined Z24S8 buffer. Reviewed-by: Eric Anholt <[email protected]>
* gallium/auxiliary: Add util_format_get_depth_only() helper.Kenneth Graunke2018-10-141-0/+21
| | | | | | | This will be used by u_transfer_helper.c shortly, in order to split packed depth-stencil into separate resources. Reviewed-by: Eric Anholt <[email protected]>
* nir: Create sampler variables in prog_to_nir.Kenneth Graunke2018-10-141-2/+13
| | | | | | | | This is needed for nir_gather_info to actually count the textures, since it operates solely on variables. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* nir: Create sampler2D variables in nir_lower_{bitmap,drawpixels}.Kenneth Graunke2018-10-142-1/+23
| | | | | | | | This is needed for nir_gather_info to actually count the new textures, since it operates solely on variables. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* spirv: Update SPIR-V json and headers to Khronos masterJason Ekstrand2018-10-132-13/+604
| | | | | | This corresponds to commit 801cca8104245c07e8cc532 on GitHub. Acked-by: Bas Nieuwenhuizen <[email protected]>
* vulkan: Update the XML and headers to 1.1.88Samuel Pitoiset2018-10-132-35/+462
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* r600/sb: Fix constant-logical-operand warning.Vinson Lee2018-10-121-1/+1
| | | | | | | | | | | | | | | | | sb/sb_bc_parser.cpp:620:27: warning: use of logical '&&' with constant operand [-Wconstant-logical-operand] if (cf->bc.op_ptr->flags && FF_GDS) ^ ~~~~~~ sb/sb_bc_parser.cpp:620:27: note: use '&' for a bitwise operation if (cf->bc.op_ptr->flags && FF_GDS) ^~ & sb/sb_bc_parser.cpp:620:27: note: remove constant to silence this warning if (cf->bc.op_ptr->flags && FF_GDS) ~^~~~~~~~~ Fixes: da977ad90747 ("r600/sb: start adding GDS support") Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* i965/miptree: Use enum instead of boolean.Rafael Antognolli2018-10-122-3/+4
| | | | | | | | | | | ISL_AUX_USAGE_NONE happens to be the same as "false", but let's do the right thing and use the enum. v2: fix intel_miptree_finish_depth too (Caio) Reviewed-by: Dylan Baker <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radv: do not support blitting surfaces for R32G32B32 formatsSamuel Pitoiset2018-10-121-0/+7
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108113 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* scons: Allow building with custom MSVC_USE_SCRIPT script.Jose Fonseca2018-10-122-0/+2
| | | | | | | | | | | | | | | | | | SCons MSVC support relies on vcvarsall.bat to extract the PATH, CPP includes, library paths, etc. And SCons also has an build env var named MSVC_USE_SCRIPT which one can use to point to alternative vcvarsall.bat script. This change exposes this MSVC_USE_SCRIPT build env variable as a SCons command line variable. This will enable using MSVC outside Program Files (e.g, network shares, etc.) This change also links advapi32 library, necessary for the Windows Registry API used by WGL state tracker, avoiding missing symbols. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radv: emit the GLC bit for SSBO loads/stores when neededSamuel Pitoiset2018-10-123-8/+22
| | | | | | | | | This fixes some new memory model tests: dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.* Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108112 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* spirv/nir: handle memory access qualifiers for SSBO loads/storesSamuel Pitoiset2018-10-124-14/+77
| | | | | | | | | | | v2: - change how the access qualifiers are accumulated v3: - duplicate members in struct_member_decoration_cb() - handle access qualifiers on variables - remove access qualifiers handling in _vtn_variable_load_store() - fix setting access qualifiers on type->array_element Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]
* anv/android: we need git_sha1.h in include pathsTapani Pälli2018-10-121-0/+1
| | | | | | Fixes: e4538b9 "anv: Implement VK_KHR_driver_properties" Signed-off-by: Tapani Pälli <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* anv: Clear WM_HZ_OP overrides in init_device_stateNanley Chery2018-10-111-0/+10
| | | | | | | | | | | | | | | | | | | | This is basically a port of commit, 3ade766684933ac84e41634429fb693f85353c11 ("i965: Disable 3DSTATE_WM_HZ_OP fields.") The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer Clear." It mentions that the packet overrides GPU state for the clear operation and needs to be reset to 0s to clear the overrides. Depending on the kernel, we may not get a context with the GPU state for this packet zeroed. Do it ourselves just in case. Prevents a number of GPU hangs when running crucible on ICL. I tried to get the exact number of hangs that occurs without this patch, but was unsuccessful. The test machine became unresponsive before completing the full run. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen10+: Initialize new fields in STATE_BASE_ADDRESSJordan Justen2018-10-111-1/+6
| | | | | | Ref: 263b584d5e4 "i965/skl: Emit extra zeros in STATE_BASE_ADDRESS on Skylake." Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* anv/gen9+: Initialize new fields in STATE_BASE_ADDRESSJordan Justen2018-10-111-0/+12
| | | | | | Ref: 263b584d5e4 "i965/skl: Emit extra zeros in STATE_BASE_ADDRESS on Skylake." Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* nir: Add a bunch of b2[if] optimizationsJason Ekstrand2018-10-111-0/+17
| | | | | | | | | | | | | | | | | | The b2f and b2i conversions always produce zero or one which are both representable in every type and size. Since b2i and b2f support all bit sizes, we can just get rid of the conversion opcode. total instructions in shared programs: 15089335 -> 15084368 (-0.03%) instructions in affected programs: 212564 -> 207597 (-2.34%) helped: 896 HURT: 0 total cycles in shared programs: 369831123 -> 369826267 (<.01%) cycles in affected programs: 2008647 -> 2003791 (-0.24%) helped: 693 HURT: 216 Reviewed-by: Ian Romanick <[email protected]>
* intel/vec4: Fix nir_op_b2[fi] with 64-bit resultJason Ekstrand2018-10-111-1/+6
| | | | | | | | | This is valid NIR but you can't actually hit this case today. GLSL IR doesn't have a bool to double opcode; it does f2d(b2f(x)). In SPIR-V we don't have any to/from bool conversion opcodes at all. However, the next commit will make us start generating it so we should be ready. Reviewed-by: Ian Romanick <[email protected]>
* intel/fs: Fix nir_op_b2[fi] with 64-bit result on Gen8 LP and Gen9 LPJason Ekstrand2018-10-111-5/+5
| | | | | | | | | | | | | | | | | | | | | | Several of the Atom GPUs have additional restrictions on alignment when moving < 64-bit source to a 64-bit destination. All of the nir_op_*2*64 code generation paths respected this, but nir_op_b2[fi] did not. Previous to commit a68dd47b911 it was not possible to generate such an instruction from the GLSL path. It may have been possible from SPIR-V, but it's not clear. The aforementioned patch converts a 64-bit nir_op_fsign into a sequence of operations including a nir_op_b2f with a 64-bit result. This "just works" everywhere except these Atom parts. This problem was not detected during normal CI testing because the Atom parts are not included in developer builds. v2 (idr): Make the patch compile, and make some cosmetic changes. Add a commit message. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108319 Fixes: a68dd47b911 "nir/algebraic: Simplify fsat of fsign" Reviewed-by: Ian Romanick <[email protected]>
* egl: Use correct shared libraries suffix on macOS.Vinson Lee2018-10-111-1/+6
| | | | | Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* mesa: Fix pack_uint_Z_FLOAT32()Illia Iorin2018-10-112-18/+9
| | | | | | | | | | | | Fixed pack_uint_Z_FLOAT32 by casting row data to float instead uint. Remove code duplicate function pack_uint_Z_FLOAT32_X24S8. Edited case in "_mesa_get_pack_uint_z_func". Now it looks like "_mesa_get_pack_float_z_func". Remove _mesa_problem call, which was added for debuging this issue. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91433 Signed-off-by: Illia Iorin <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel: Introducing Whiskey Lake platformRodrigo Vivi2018-10-114-6/+8
| | | | | | | | | | | | | | | | | | | Whiskey Lake uses the same gen graphics as Coffe Lake, including some ids that were previously marked as reserved on Coffe Lake, but that now are moved to WHL page. This follows the ids and approach used on kernel's commit b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform") and commit c1c8f6fa731b ("drm/i915: Redefine some Whiskey Lake SKUs") v2: Lionel noticed that GT{1,2,3} on kernel wasn't following spec when looking to number of EUs, so kernel has been updated. Cc: Lionel Landwerlin <[email protected]> Cc: José Roberto de Souza <[email protected]> Cc: Anuj Phogat <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* st/va: use provided sizes and coords for vlVaGetImageBoyuan Zhang2018-10-111-3/+28
| | | | | | | | | | | | | | | | vlVaGetImage should respect the width, height, and coordinates x and y that passed in. Therefore, pipe_box should be created with the passed in values instead of surface width/height. v2: add input size check, return error when size out of bounds v3: fix the size check for vaimage v4: add size adjustment for x and y coordinates Signed-off-by: Boyuan Zhang <[email protected]> Cc: "18.2" <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Acked-by: Christian König <[email protected]>
* radv: implement clear operations for R32G32B32Samuel Pitoiset2018-10-113-1/+284
| | | | | | | | | | This fixes crashes for some CTS: dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.*.linear_*_* dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.*.*_linear_* Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108113 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: disallow 3D images and mipmaps/layers for R32G32B32 linear formatsSamuel Pitoiset2018-10-111-0/+14
| | | | | | | | R32G32B32 are weird formats and we are only going to support some basic operations for now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add a workaround for a VGT hang with prim restart and stripsSamuel Pitoiset2018-10-111-0/+11
| | | | | | | | | | | Otherwise, Yakuza and The Evil Within hang the GPU with DXVK. This apparently only works on Polaris. Suggested by Marek. Cc: [email protected] Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* glsl: remove redundant es_shader checksTimothy Arceri2018-10-112-5/+1
| | | | | | The es check is already covered by the is_version() check. Reviewed-by: Ian Romanick <[email protected]>
* st/glsl_to_tgsi: initialise need_uarl in contructorDave Airlie2018-10-111-0/+1
| | | | | | Found by coverity Reviewed-by: Marek Olšák <[email protected]>
* glspirv: drop pointless assert (size_t is unsigned)Dave Airlie2018-10-111-2/+0
| | | | | | Found by coverity Reviewed-by: Alejandro Piñeiro <[email protected]>
* radv: remove unsigned comparison against 0Dave Airlie2018-10-111-1/+1
| | | | | | | | The value is always >= 0 here. Found by coverity Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: remove dead code for master_fd closeDave Airlie2018-10-111-2/+0
| | | | | | | | | We have never opened master_Fd at this point, so remove code to close it. Found by coverity. Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: don't pass shader key by copyDave Airlie2018-10-111-7/+6
| | | | | | Coverity pointed out we were copying 168 bytes here unnecessarily. Reviewed-by: Samuel Pitoiset <[email protected]>
* anv: add missing unlock in error path.Dave Airlie2018-10-111-0/+1
| | | | | | | | | | Not going to matter, but be consistent. Found by coverity Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Fixes: caf41c78c (anv/allocator: Support softpin in the BO cache)
* intel: Don't propagate conditional modifiers if a UD source is negatedJason Ekstrand2018-10-105-0/+50
| | | | | | | | | This fixes a bug uncovered by my NIR integer division by constant optimization series. Fixes: 19f9cb72c8b "i965/fs: Add pass to propagate conditional..." Fixes: 627f94b72e0 "i965/vec4: adding vec4_cmod_propagation..." Reviewed-by: Ian Romanick <[email protected]>
* util: Add tests for fast integer division by constantsJason Ekstrand2018-10-105-0/+547
| | | | | | | | | While I generally trust rediculousfish to have done his homework, we've made some adjustments to suit the needs of mesa and it'd be good to test those. Also, there's no better place than unit tests to clearly document the different edge cases of the different methods. Reviewed-by: Marek Olšák <[email protected]>
* util: Add power-of-two divisor support to compute_fast_udiv_infoMarek Olšák2018-10-102-2/+23
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* util: Generalize fast integer division to be variable bit-widthJason Ekstrand2018-10-102-45/+39
| | | | | | | | | | | | | | | There's nothing inherently fixed-width in the code. All that's required to generalize it is to make everything internally 64-bit and pass UINT_BITS in as a parameter to util_compute_fast_[us]div_info. With that, it can now handle 8, 16, 32, and 64-bit integer division by a constant. We also add support for division by 1 and by other powers of 2. This is useful if you want to divide by a uniform value in a shader where you have the opportunity to adjust the uniform on the CPU before passing it in. Reviewed-by: Marek Olšák <[email protected]>
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