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* radeonsi: remove some definitions and helpers from r600_pipe_common.hMarek Olšák2017-11-2913-136/+125
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't use fast color clear for small surfacesMarek Olšák2017-11-291-0/+17
| | | | | | This removes 35+ clear eliminate passes from DOTA 2. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: unify code setting dirty_level_mask for fast clearMarek Olšák2017-11-291-14/+11
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clean up si_do_fast_color_clear parametersMarek Olšák2017-11-291-10/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove r600_common_context::clear_bufferMarek Olšák2017-11-295-20/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move r600_test_dma.c into si_test_dma.cMarek Olšák2017-11-298-20/+20
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move si_pipe_clear_buffer into si_cp_dma.cMarek Olšák2017-11-292-61/+61
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move all clear() code into si_clear.cMarek Olšák2017-11-299-719/+764
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable DCC with MSAA for VIMarek Olšák2017-11-295-2/+15
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: implement fast color clear for DCC with MSAA for VIMarek Olšák2017-11-291-5/+30
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add a workaround for blending with DCC and MSAAMarek Olšák2017-11-291-8/+23
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clear PIPE_IMAGE_ACCESS_WRITE when it's invalid to be on the safe sideMarek Olšák2017-11-291-0/+10
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: enable DCC computation for MSAAMarek Olšák2017-11-293-6/+6
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix layered DCC fast clearMarek Olšák2017-11-291-1/+4
| | | | | Cc: 17.2 17.3 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* util: Also include endian.h on cygwinJon Turney2017-11-291-1/+1
| | | | | | | | If u_endian.h can't determine the endianess, the default behaviour in sha1.c is to build for big-endian Signed-off-by: Jon Turney <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: deal with vs_inputs as 64-bit unsigned integerJuan A. Suarez Romero2017-11-291-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 78942e ("mesa: shrink VERT_ATTRIB bitfields to 32 bits") uses vs_prog_data->vs_inputs as if it were a 32-bit unsigned integer. But actually it is a 64-bit integer, and as such it is used in other parts of Mesa code. It is worth to note that bits from the entire range are used, and not only 32-bits. This is due our implementation for handling 64-bit dual-slot input attributes, which requires to use a larger bitfield to manage them. This commit reverts the changes done in brw_draw_upload.c, keeping the rest of the changes. This fixes the following tests: - KHR-GL45.enhanced_layouts.varying_array_locations - KHR-GL45.enhanced_layouts.varying_locations Fixes: 78942e ("mesa: shrink VERT_ATTRIB bitfields to 32 bits") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103942 CC: Marek Olšák <[email protected]> CC: Ian Romanick <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Juan A. Suarez Romero <[email protected]>
* mesa: rework _mesa_add_parameter() to only add a single paramTimothy Arceri2017-11-293-39/+41
| | | | | | | | | This is more inline with what the functions name suggests it should do, and makes the code much easier to follow. This will also make adding uniform packing support much simpler. Reviewed-by: Nicolai Hähnle <[email protected]>
* r600: lds load cleanups.Dave Airlie2017-11-291-6/+8
| | | | | | This is just some cleanups on top of the last patch from my compute branch. Signed-off-by: Dave Airlie <[email protected]>
* r600_shader: only load from LDS what is really usedGert Wollny2017-11-291-7/+26
| | | | | | | | Use the destination write mask to determine which values are really to be read from LDS and load only these. Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Gert Wollny <[email protected]>
* r600/sb: handle jump after target to end of program. (v2)Dave Airlie2017-11-291-0/+5
| | | | | | | | | | | | | | | | This fixes hangs on cayman with tests/spec/arb_tessellation_shader/execution/trivial-tess-gs_no-gs-inputs.shader_test This has a single if/else in it, and when this peephole activated, it would set the jump target to NULL if there was no instruction after the final POP. This adds a NOP if we get a jump in this case, and seems to fix the hangs, so we have a valid target for the ELSE instruction to go to, instead of 0 (which causes infinite loops). v2: update last_cf correctly. (I had some other patches hide this) Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: Change a ret == -1 check to ret != 0.Kenneth Graunke2017-11-281-1/+1
| | | | | | For consistency with most other ret checks. Suggested by Chris. Reviewed-by: Chris Wilson <[email protected]>
* i965: Use C99 struct initializers in brw_bufmgr.c.Kenneth Graunke2017-11-281-91/+49
| | | | | | | | | | This is cleaner than using a non-standard memclear macro (which does a memset to 0) and then initializing fields after the fact. We move the declarations to where we initialized the fields. While we're at it, we move the declaration of 'ret' that goes with the ioctl, eliminating the declaration section altogether. Reviewed-by: Chris Wilson <[email protected]>
* i965: Move perf_debug and WARN_ONCE back to brw_context.h.Kenneth Graunke2017-11-282-29/+29
| | | | | | | | These were moved to src/intel/common/gen_debug.h, but they are not common code. They assume that brw_context or gl_context variables exist, named brw or ctx. That isn't remotely true outside of i965. Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: const a few structs and vars to avoid writing to them by accidentEric Engestrom2017-11-281-4/+4
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix Smooth Point Enables.Kenneth Graunke2017-11-281-1/+1
| | | | | | | | | | We want to program the 3DSTATE_RASTER field to the gl_context value, not the other way around. Fixes: 13ac46557ab1 (i965: Port Gen8+ 3DSTATE_RASTER state to genxml.) Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* meson: build virgl driverDylan Baker2017-11-286-6/+114
| | | | | | | Build tested only. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: build svga driver on linuxDylan Baker2017-11-285-3/+146
| | | | | | | Build tested only. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: build r600 driverDylan Baker2017-11-286-11/+155
| | | | | | | | | v4: - Ensure inc_amd_common defined when radeonsi is disabled (needed by r600) Signed-off-by: Dylan Baker <[email protected]> Tested-by: Aaron Watry <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: build r300 driverDylan Baker2017-11-284-7/+176
| | | | | | | This is build tested only Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: build i915g driverDylan Baker2017-11-285-4/+116
| | | | | | | Build tested only. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* svga: move svga_is_format_supported() to svga_format.cBrian Paul2017-11-283-121/+129
| | | | | | where the other format-related functions live. Reviewed-by: Charmaine Lee <[email protected]>
* svga: s/unsigned/SVGA3dDevCapIndex/Brian Paul2017-11-281-3/+6
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* i965: perf: add support for CoffeeLake GT3Lionel Landwerlin2017-11-285-2/+10712
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: perf: add support for CoffeeLake GT2Lionel Landwerlin2017-11-285-2/+10484
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: perf: add busyness metric sets on gen8/9 platformsLionel Landwerlin2017-11-287-0/+1231
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: fix time elapsed counter equations in VME/Media configsLionel Landwerlin2017-11-286-12/+12
| | | | | | | | There was a mistake just in those metric sets. We probably didn't noticed because they're not really interesting for 3D workloads. Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: perf: update counter names on gen8/9 platformsLionel Landwerlin2017-11-288-116/+116
| | | | | | | Just fixing names. Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: add a debug option to disable oa config loadingLionel Landwerlin2017-11-283-2/+4
| | | | | | | | | This provides a good way to verify we haven't broken using the perf driver on older kernels (which don't have the oa config loading mechanism). Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: perf: add support for userspace configurationsLionel Landwerlin2017-11-281-8/+101
| | | | | | | | | | This allows us to deploy new configurations without touching the kernel. v2: Detect loadable configs without creating one (Chris) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: perf: update configs for loading from userspaceLionel Landwerlin2017-11-2810-0/+243
| | | | | | | | | | When making configs loadable from userspace in the kernel, we left to userspace more responsability around programming some registers. In particular one register we use to set directly in the driver has now been moved into the configs. Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* util: add mesa-sha1 test to mesonEric Engestrom2017-11-281-0/+9
| | | | | | Fixes: 513d7ffa23d42e96f831 "util: Add a SHA1 unit test program" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* compiler: fix typoEric Engestrom2017-11-281-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* compiler: use NDEBUG to guard assertsEric Engestrom2017-11-283-6/+6
| | | | | | | | | nir_validate.c's #endif already had the correct NDEBUG comment Fixes: dcb1acdea00a8f2c29777 "nir/validate: Only build in debug mode" Fixes: 9ff71b649b4b3808a9e17 "i965/nir: Validate that NIR passes call nir_metadata_preserve()" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* broadcom: use NDEBUG to guard assertsEric Engestrom2017-11-281-5/+5
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* vc4: check preprocessor token existence using #ifdef instead of #ifEric Engestrom2017-11-281-3/+3
| | | | | | | (other uses of USE_VC4_SIMULATOR are already correct) Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* docs/llvmpipe.html: Minor editsBen Crocker2017-11-281-7/+7
| | | | | | | | | | | Language and spelling fixups in three places. Cc: "17.2" "17.3" <[email protected]> Signed-off-by: Ben Crocker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> [Eric: move two fixes from the other patch to this one.] Signed-off-by: Eric Engestrom <[email protected]>
* st/dri: replace hard-coded array size with ARRAY_SIZE()Eric Engestrom2017-11-281-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/gfx9: simplify condition for on-chip ESGSNicolai Hähnle2017-11-281-3/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: clarify that si_shader_selector::esgs_itemsize is set for the ES partNicolai Hähnle2017-11-281-1/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use si_shader_context instead of lp_build_context in more placesNicolai Hähnle2017-11-281-27/+23
| | | | Reviewed-by: Marek Olšák <[email protected]>
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