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* nir/repair_ssa: Repair dominance for unreachable blocksJason Ekstrand2019-09-061-4/+8
| | | | | | | | | | | | NIR currently assumes that unreachable blocks are trivially dominated by everything. However, when considering well-formed SSA, there is no path from any block to an unreachable block. Therefore, we can break any use-def chains where the use is in an unreachable block. This removes any dependencies on code created by uses in unreachable blocks and lets DCE do a better job of cleaning it up. Cc: [email protected] Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* nir: Add a block_is_unreachable helperJason Ekstrand2019-09-062-0/+15
| | | | | Cc: [email protected] Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* nir: Don't infinitely recurse in lower_ssa_defs_to_regs_blockJason Ekstrand2019-09-061-5/+15
| | | | | Cc: [email protected] Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* nir: Handle complex derefs in nir_split_array_varsJason Ekstrand2019-09-061-2/+5
| | | | | | | | We already bail and don't split the vars but we were passing a NULL to _mesa_hash_table_search which is not allowed. Fixes: f1cb3348f1 "nir/split_vars: Properly bail in the presence of ..." Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/blorp: Use wide formats for nicely aligned stencil clearsJason Ekstrand2019-09-062-0/+122
| | | | | | | | | | | | | | | | In the case where the stencil clear is nicely aligned, we can clear stencil much more efficiently by mapping it as a wide format (say RGBA32_UINT) and blasting out the stencil clear value with a repclear. On Unigine Heaven, this makes one stencil clear go from non-trivial to unnoticeable when looking at per-draw timings. In order for this change to work properly, ANV needs to do a bit more flushing around depth and stencil clears. i965 and iris already have the cache tracking logic to handle this so no changes are required there. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/blorp: Expose surf_fake_interleaved_msaa internallyJason Ekstrand2019-09-062-5/+8
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* intel/blorp: Expose surf_retile_w_to_y internallyJason Ekstrand2019-09-062-5/+8
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* blorp: Memset surface info to zero when initializing itJason Ekstrand2019-09-061-0/+1
| | | | | | | | This isn't known to fix any current bugs but it does prevent a regression in a subsequent commit. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/tools: Decode PS kernels on SNBJason Ekstrand2019-09-061-1/+4
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/tools: Decode 3DSTATE_BINDING_TABLE_POINTERS on SNBJason Ekstrand2019-09-061-0/+15
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* nir/lower_io_to_vector: don't merge compact varyingsRhys Perry2019-09-061-0/+3
| | | | | | Signed-off-by: Rhys Perry <[email protected]> Fixes: 02bc4aabb48 ('nir/lower_io_to_vector: allow FS outputs to be vectorized') Reviewed-by: Kenneth Graunke <[email protected]>
* drirc: override minImageCount=2 for gfxbenchEric Engestrom2019-09-061-0/+4
| | | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110765 Fixes: 4689e98fe884d9412b72 ("vulkan/wsi: Set X11 minImageCount to 3.") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Eero Tamminen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* radv: add support for vk_x11_override_min_image_countEric Engestrom2019-09-061-0/+1
| | | | | | | Cc: [email protected] Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* amd: move adaptive sync to performance section, as it is defined in xmlpoolEric Engestrom2019-09-062-5/+2
| | | | | | | | Fixes: 3844ed8d44677588bc29 ("radv: Add adaptive_sync driconfig option and enable it by default.") Fixes: e260493f2ab2483e5a55 ("radeonsi: Enable adaptive_sync by default for radeon") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: add support for vk_x11_override_min_image_countEric Engestrom2019-09-061-0/+3
| | | | | | | Cc: [email protected] Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* wsi: add minImageCount overrideEric Engestrom2019-09-065-3/+27
| | | | | | | Cc: [email protected] Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (v1) Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: add support for driconfEric Engestrom2019-09-064-3/+19
| | | | | | | | | No option is supported yet, this is just the boilerplate. Cc: [email protected] Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* gallivm: drop LLVM<3.3 code paths as no build system allows thatEric Engestrom2019-09-065-42/+36
| | | | | Suggested-by: Michel Dänzer <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* meson/scons/android: drop now-unused HAVE_LLVMEric Engestrom2019-09-063-15/+7
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* llvmpipe: replace more complex 3.x version check with LLVM_VERSION_MAJOR/MINOREric Engestrom2019-09-061-2/+3
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* clover: replace more complex 3.x version check with LLVM_VERSION_MAJOR/MINOREric Engestrom2019-09-061-2/+3
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* gallivm: replace more complex 3.x version check with LLVM_VERSION_MAJOR/MINOREric Engestrom2019-09-067-71/+74
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* clover: replace major llvm version checks with LLVM_VERSION_MAJOREric Engestrom2019-09-062-17/+19
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* gallivm: replace major llvm version checks with LLVM_VERSION_MAJOREric Engestrom2019-09-068-26/+34
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* swr: replace major llvm version checks with LLVM_VERSION_MAJOREric Engestrom2019-09-061-3/+4
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* amd: replace major llvm version checks with LLVM_VERSION_MAJOREric Engestrom2019-09-0610-26/+39
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* svga: replace binary HAVE_LLVM checks with LLVM_AVAILABLEEric Engestrom2019-09-061-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* r600: replace binary HAVE_LLVM checks with LLVM_AVAILABLEEric Engestrom2019-09-061-6/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* aux/draw: replace binary HAVE_LLVM checks with LLVM_AVAILABLEEric Engestrom2019-09-068-26/+26
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* meson/scons/android: add LLVM_AVAILABLE binary flagEric Engestrom2019-09-063-4/+6
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* gallivm: replace `0x` version print with actual version stringEric Engestrom2019-09-061-2/+3
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* anv,iris: L3ALLOC register replaces L3CNTLREG for gen12Jordan Justen2019-09-063-9/+29
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/gen12: Add L3 configurationsAnuj Phogat2019-09-061-1/+12
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* util: include u_endian.h in u_math.hRhys Perry2019-09-061-0/+1
| | | | | | | | | | | | u_endian.h needs to be included, otherwise PIPE_ARCH_BIG_ENDIAN might not be defined on big-endian architectures and the endian conversion macros will be incorrect. I don't think anything is broken because of this, I just noticed this when looking at the file. Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* anv: Bump maxComputeWorkgroupSizeJason Ekstrand2019-09-061-4/+6
| | | | | | Fixes: 9a129510f56f "anv: Bump maxComputeWorkgroupInvocations" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111552 Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: Stop redirecting state cache to command streamer cache sectionKenneth Graunke2019-09-063-23/+0
| | | | | | | | | | | | | | | | | | This bit redirects the state cache from the unified/RO sections of the L3 cache to the "CS command buffer" section of the cache, which would be set up via TCCNTLREG. The documentation says: "Additionaly, this redirection should be enabled only if there is a non-zero allocation for the CS command buffer section." We don't allocate any cache to the CS command buffer section, so enabling this redirection effectively disabled the state cache. The Windows driver only sets up that section when using POSH, which we do not currently use. So, leave it unallocated and disable the redirection to get a functional state cache again. Improves performance in Civilization VI by 18%, Manhattan 3.0 by 6%, and Car Chase by 2%.
* iris: Invalidate state/texture/constant caches after STATE_BASE_ADDRESSKenneth Graunke2019-09-061-4/+55
| | | | | | | | Jason pointed out that the caches likely refer to offsets from dynamic and surface state base addresses, so when we change those, we need to invalidate the caches. Comment borrowed from src/intel/vulkan/genX_cmd_buffer.c.
* freedreno/a6xx: Implement primitive count queries on GPUKristian H. Kristensen2019-09-0615-18/+128
| | | | | | | | | | The driver can't determine PIPE_QUERY_PRIMITIVES_GENERATED or PIPE_QUERY_PRIMITIVES_EMITTED once we support geometry or tessellation, since these stages add primitives at runtime. Use the WRITE_PRIMITIVE_COUNTS event to write back the primitive counts and implement a hw query for this. Reviewed-by: Rob Clark <[email protected]>
* freedreno/a6xx: Let the GPU track streamout offsetsKristian H. Kristensen2019-09-064-19/+36
| | | | | | | | | | The GPU writes out streamout offsets as it goes to the FLUSH_BASE pointer. We use that value with CP_MEM_TO_REG when appending to the stream so that we don't have to track the offsets with the CPU in the driver. This ensures that streamout continues to work once we enable geometry and tessellation shader stages that add geometry. Reviewed-by: Rob Clark <[email protected]>
* llvmpipe: fix CALLOC vs. free mismatchesRoland Scheidegger2019-09-062-4/+5
| | | | | | | Should fix some issues we're seeing. And use REALLOC instead of realloc. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* radv/gfx10: determine the number of vertices per primitive for TESSamuel Pitoiset2019-09-061-1/+16
| | | | | | | This doesn't fix anything known but it's correct now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir/lower_io_to_vector: add flat modeRhys Perry2019-09-061-47/+204
| | | | | | | | | | | | | | | | | | | | | This has lower_io_to_vector try to turn variables into arrays of 4-sized vectors when possible and fall back to the old approach when that isn't possible. This is so that lower_io_to_vector can guarantee that only one variable is used for each fragment shader output. v2: handle dual-source blending v3: don't try to merge structs and non-32-bit types in get_flat_type() v3: fix per-vertex inputs v3: fix and cleanup location advancement in get_flat_type() and it's calling code v4: prioritize the original mode over the flat mode v4: don't create flat variables to merge only one variable v5: don't skip an entire slot when encountering structs in the old mode Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* nir/lower_io_to_vector: allow FS outputs to be vectorizedRhys Perry2019-09-062-27/+33
| | | | | | | | v2: handle dual-source blending v3: use a higher MAX_SLOTS Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* radv/gfx10: make use the output usage mask when exporting NGG GS paramsSamuel Pitoiset2019-09-061-3/+8
| | | | | | | | | It shouldn't matter much because output varyings should have been compacted during NIR shader linking but it mirrors what the driver does when emitting NGG GS vertex parameters. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: account for the subpass view for the NGG GS storageSamuel Pitoiset2019-09-061-0/+3
| | | | | | | | | If the fragment shader needs the layer index, we have to allocate one more dword in the NGG GS storage. Found by inspection. This doesn't fix anything known. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* panfrost/ci: Increase timeoutsTomeu Vizoso2019-09-061-2/+2
| | | | | | | | Sometimes LAVA jobs will timeout due to transient issues, and the Gitlab job will fail in that case. Increase the timeouts to reduce the likeliness of that happening and reduce false positives. Signed-off-by: Tomeu Vizoso <[email protected]>
* panfrost/ci: Use special runner for LAVA jobsTomeu Vizoso2019-09-061-9/+1
| | | | | | | So repositories don't need to be specially configured with a token to access LAVA, store this token in a bind volume for a special runner. Signed-off-by: Tomeu Vizoso <[email protected]>
* panfrost/ci: Re-add support for armhfTomeu Vizoso2019-09-064-28/+39
| | | | | | | Now that Volt supports armhf, build again images and submit to LAVA for RK3288. Signed-off-by: Tomeu Vizoso <[email protected]>
* radv: calculate esgs_itemsize in the shader info passSamuel Pitoiset2019-09-062-14/+20
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: calculate the GSVS vertex size in the shader info passSamuel Pitoiset2019-09-062-15/+11
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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