summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* radeonsi/gfx10: add as_ngg shader key bitNicolai Hähnle2019-07-033-10/+42
| | | | | | | Also add the shader main part NGG variant, so that in principle we can switch between legacy in NGG modes. Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: implement si_update_shadersNicolai Hähnle2019-07-031-50/+62
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: implement si_build_vgt_shader_configNicolai Hähnle2019-07-032-2/+14
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: keep track of whether NGG is usedNicolai Hähnle2019-07-034-1/+31
| | | | | | | We always use NGG by default, except when tessellation is enabled with extreme geometry shader amplification. Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: document NGG shader stagesNicolai Hähnle2019-07-031-10/+15
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: implement gfx10_emit_cache_flushNicolai Hähnle2019-07-034-3/+195
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: add si_context::emit_cache_flushNicolai Hähnle2019-07-039-9/+15
| | | | | | | | | | | The introduction of GCR_CNTL makes cache flush handling on gfx10 sufficiently different that it makes sense to just use a separate function. Since emit_cache_flush is called quite early during context init, we initialize the pointer explicitly in si_create_context. Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: implement DB registersNicolai Hähnle2019-07-033-13/+56
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: set CB registersNicolai Hähnle2019-07-032-5/+76
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: always set up sample locationsNicolai Hähnle2019-07-031-1/+5
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: use Z32_FLOAT_CLAMP for upgraded depth texturesNicolai Hähnle2019-07-032-10/+22
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: implement vertex format changesNicolai Hähnle2019-07-032-6/+23
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: implement si_set_{constant,shader}_bufferNicolai Hähnle2019-07-031-6/+20
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: implement si_make_buffer_descriptorNicolai Hähnle2019-07-031-10/+28
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: implement si_set_mutable_tex_desc_fieldsNicolai Hähnle2019-07-031-5/+30
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: gfx10 can render up to 8192 layersNicolai Hähnle2019-07-031-0/+4
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: add gfx10_make_texture_descriptorNicolai Hähnle2019-07-031-1/+187
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: add pipe_screen::make_texture_descriptorNicolai Hähnle2019-07-035-16/+19
| | | | | | Texture descriptors in gfx10 are very different. Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: determine view->is_integer based on the pipe_formatNicolai Hähnle2019-07-031-6/+15
| | | | | | It was convenient, but NUM_FORMAT no longer exists in gfx10. Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: implement si_is_format_supportedNicolai Hähnle2019-07-031-0/+17
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: generate gfx10_format_table.hNicolai Hähnle2019-07-035-2/+300
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: set MAX_ALLOC_COUNTNicolai Hähnle2019-07-031-2/+14
| | | | | | The number for Vega was copied from PAL and has no effect because of MIN2. Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: require LLVM 9Nicolai Hähnle2019-07-031-0/+6
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: update for new vcn enc interfaceBoyuan Zhang2019-07-032-1/+4
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: enable jpeg decode for navi10Boyuan Zhang2019-07-031-1/+2
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: implement vcn 2.0 jpeg decodeBoyuan Zhang2019-07-031-56/+157
| | | | | | | Use direct register to implement vcn 2.0 jpeg deocde Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: add direct register boolBoyuan Zhang2019-07-032-0/+3
| | | | | | | VCN 2.0 uses direct register space where VCN 1.0 uses some indirect registers Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: add defines for vcn 2.0 jpegBoyuan Zhang2019-07-031-0/+25
| | | | | | | Add neccesary register defines for vcn 2.0 jpeg deocde Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: use variable to assign ib cmdBoyuan Zhang2019-07-033-40/+128
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: implement vcn 2.0 encodeBoyuan Zhang2019-07-034-5/+220
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: add vcn2.0 encode skeletonBoyuan Zhang2019-07-034-0/+81
| | | | | | Signed-off-by: Boyuan Zhang <[email protected]> (v2: build fix -- Nicolai) Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: move vcn1.0 specific defines to cBoyuan Zhang2019-07-032-29/+29
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: assign function pointer with ib functionsBoyuan Zhang2019-07-033-165/+182
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: add function pointer for ib functionsBoyuan Zhang2019-07-031-0/+32
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: move header related algorithm to vcn_encBoyuan Zhang2019-07-033-122/+142
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: move add buf func to common fileBoyuan Zhang2019-07-033-16/+17
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: move cs defines to enc header fileBoyuan Zhang2019-07-032-10/+10
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: add VP9 support for Navi10Leo Liu2019-07-031-10/+20
| | | | | | | It requires bigger DPB and context buffers Signed-off-by: Leo Liu <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: enable encode support for newer HWLeo Liu2019-07-031-5/+3
| | | | | | | Previously it was Raven only allowed to do so Signed-off-by: Leo Liu <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeon/vcn: add VCN2 set of internal registers for IBLeo Liu2019-07-032-9/+31
| | | | | | | | From VCN2.0, the RBC have different views on the registers Signed-off-by: Leo Liu <[email protected]> (v2: rebase -- Nicolai) Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/uvd: allow newer HW to create HW decoderLeo Liu2019-07-031-2/+1
| | | | | | | Previously it was Raven only allowed to do so Signed-off-by: Leo Liu <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* ac/surface/gfx10: allow "rotated" micro modeNicolai Hähnle2019-07-032-8/+8
| | | | | | | | Standard mode does not support DCC. The R is retconned to "render target" on gfx10. Acked-by: Bas Nieuwenhuizen <[email protected]>
* ac/surface/gfx10: DCC is only supported with SW_64KB_{Z,R}_X modesNicolai Hähnle2019-07-031-3/+10
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* amd/addrlib/gfx10: forbid DCC for swizzle modes which the hardware does not ↵Nicolai Hähnle2019-07-031-3/+2
| | | | | | support Acked-by: Bas Nieuwenhuizen <[email protected]>
* amd/addrlib/gfx10: fix assertion in Addr2IsValidDisplaySwizzleModeNicolai Hähnle2019-07-031-0/+1
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* amd/common/gfx10: print gfx10 registers in debug dumpsNicolai Hähnle2019-07-031-1/+3
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* amd/common/gfx10: CMASK is only used for FMASKNicolai Hähnle2019-07-031-2/+3
| | | | | | All regular color compression is done via DCC. Acked-by: Bas Nieuwenhuizen <[email protected]>
* amd/common/gfx10: support new tbuffer encodingNicolai Hähnle2019-07-031-2/+45
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* amd/common/gfx10: pad shader buffers for instruction prefetchNicolai Hähnle2019-07-031-0/+19
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* amd/common/gfx10: implement scan & reduce operationsNicolai Hähnle2019-07-031-8/+104
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 09:41:58 +0000