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* | radeon/llvm: Remove AMDGPUConstants.pmTom Stellard2012-05-092-45/+23
* | radeon/llvm: Don't rely on tablegen for lowering int_AMDGPU_load_constTom Stellard2012-05-095-38/+20
* | radeon/llvm: Make sure the LOAD_CONST def uses the isSI predicateTom Stellard2012-05-092-7/+7
* | svga: implement CEIL opcode translationBrian Paul2012-05-091-0/+28
* | glsl_to_tgsi: use TGSI_OPCODE_CEIL for ir_unop_ceilChristoph Bumiller2012-05-091-3/+1
* | gallium/drivers: handle TGSI_OPCODE_CEILChristoph Bumiller2012-05-094-0/+28
* | r600g: Handle TGSI_OPCODE_CEIL (v2)Kai Wasserbäch2012-05-091-3/+3
* | gallivm: implement iabs/issg opcode.Dave Airlie2012-05-092-1/+26
* | i965: fix wrong cube/3D texture layoutYuanhan Liu2012-05-091-2/+3
* | radeon/llvm: Remove AMDILUtilityFunctions.cppTom Stellard2012-05-0813-1041/+399
* | radeon/llvm: Remove some unused functions from AMDILInstrInfoTom Stellard2012-05-082-164/+0
* | radeon/llvm: Add some comments and fix coding styleTom Stellard2012-05-088-42/+41
* | radeon/llvm: Remove the EXPORT_REG instructionTom Stellard2012-05-0810-117/+8
* | radeon/llvm: Use a custom inserter to lower RESERVE_REGTom Stellard2012-05-0810-27/+83
* | radeon/llvm: Use a custom inserter to lower STORE_OUTPUTTom Stellard2012-05-084-34/+23
* | radeon/llvm: Remove AMDGPULowerShaderInstructions classTom Stellard2012-05-086-86/+4
* | radeon/llvm: Use a custom inserter to lower LOAD_INPUTTom Stellard2012-05-084-39/+15
* | radeon/llvm: Remove the ReorderPreloadInstructions passTom Stellard2012-05-089-100/+4
* | radeon/llvm: Remove old comment from AMDIL.hTom Stellard2012-05-081-5/+0
* | Add bin/compile to .gitignorePaul Berry2012-05-081-0/+1
* | glsl: Change built-in constant expression evaluation to run the IR.Olivier Galibert2012-05-082-380/+156
* | glsl: Add an origin pointer in the function signature object.Olivier Galibert2012-05-083-0/+5
* | glsl: Add methods to copy parts of one ir_constant into another.Olivier Galibert2012-05-082-0/+114
* | glsl: Add a constant_referenced method to ir_dereference*Olivier Galibert2012-05-082-0/+128
* | glsl: Add a variable context to constant_expression_value().Olivier Galibert2012-05-083-31/+44
* | glsl: Extend ir_constant::zero to handle more types.Olivier Galibert2012-05-081-1/+16
* | glsl: Fix broken constant expression handling for <, <=, >, and >=.Kenneth Graunke2012-05-081-9/+9
* | vbo: add some commentsBrian Paul2012-05-082-1/+7
* | mesa: remove needless casts in save_EdgeFlag()Brian Paul2012-05-081-1/+1
* | mesa: minor clean-ups in dlist material codeBrian Paul2012-05-081-7/+15
* | mesa: fix error strings in dlist codeBrian Paul2012-05-081-4/+4
* | mesa: add gl_context::NewDriverState and use it for vertex arraysMarek Olšák2012-05-0813-8/+46
* | mesa: move gl_client_array*[] from vbo_draw_func into gl_contextMarek Olšák2012-05-0818-31/+61
* | vbo: move vbo_draw_method into vbo_context.hMarek Olšák2012-05-085-40/+38
* | radeon/llvm: add suport for cube texturesVadim Girlin2012-05-082-23/+91
* | radeon/llvm: add support for CUBE ALU instructionVadim Girlin2012-05-085-21/+63
* | radeon/llvm: add support for some ALU instructionsVadim Girlin2012-05-084-13/+293
* | radeon/llvm: add missing cases for BREAK/CONTINUEVadim Girlin2012-05-082-0/+3
* | radeon/llvm: add support for AHSR/LSHR/LSHL instructionsVadim Girlin2012-05-084-0/+53
* | radeon/llvm: add support for TXQ/TXF/DDX/DDY instructionsVadim Girlin2012-05-086-6/+43
* | radeon/llvm: add support for VertexID, InstanceIDVadim Girlin2012-05-083-0/+50
* | radeon/llvm: fix live-in handling for inputsVadim Girlin2012-05-082-2/+3
* | radeon/llvm: add support for v4i32Vadim Girlin2012-05-084-5/+20
* | radeon/llvm: fix ABS_i32 instruction loweringVadim Girlin2012-05-081-2/+2
* | radeon/llvm: use integer comparison for IFVadim Girlin2012-05-081-2/+4
* | radeon/llvm: use bitcasts for integersVadim Girlin2012-05-083-5/+73
* | r600g: Fix out of tree builds that use the LLVM backendTom Stellard2012-05-071-1/+1
* | radeon/llvm: Remove references to DebugFlag and isCurrentDebugType()Tom Stellard2012-05-074-22/+3
* | i965/Gen7: Work around GPU hangs due to misaligned depth coordinate offsets.Paul Berry2012-05-072-0/+54
* | i965/Gen6: Work around GPU hangs due to misaligned depth coordinate offsets.Paul Berry2012-05-072-0/+54
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