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* freedreno/a5xx: fix (at least some) vtx formatsRob Clark2016-12-181-1/+1
| | | | | | | | | Swap/component-order doesn't seem to be quite what that is. At least blob was always setting it to XYZW ('11') but we weren't. Causing problems w/ formats like sint16.. Hard-coding this instead at least seems to get glamor working. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: more formatsRob Clark2016-12-181-25/+25
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: fixup capsRob Clark2016-12-182-6/+11
| | | | | | | | | | Might not be 100% accurate, mostly just copy from a4xx to get started. We are defn lying about occlusion query at this point (not implemented yet) but need it to expose anything higher than gl1.4 (glamor needs gl2.1) Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: fix random faults on first sysmem drawRob Clark2016-12-181-0/+3
| | | | | | | | Not sure what this event is, but blob writes it.. and it seems to solve random write faults at mystery address that would sometimes happen on first BYPASS draw. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2016-12-186-17/+80
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: fix stride/size for mem->gmem blitsRob Clark2016-12-181-5/+7
| | | | | | <brownpaperbag>these should be the in-GMEM dimensions</brownpaperbag> Signed-off-by: Rob Clark <[email protected]>
* radv/winsys: consolidate request->fence codeDave Airlie2016-12-171-22/+19
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: handle fence allocation failingDave Airlie2016-12-171-1/+4
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Don't bail out on pipeline create failure.Bas Nieuwenhuizen2016-12-171-21/+17
| | | | | | | | | | | | | | The spec says we have to try to create all, and only set failed pipelines to VK_NULL_HANDLE. If one of them fails, we have to return an error, but as far as I can see, the spec does not care which of the suberrors. Fixes dEQP-VK.api.object_management.alloc_callback_fail_multiple.compute_pipeline dEQP-VK.api.object_management.alloc_callback_fail_multiple.graphics_pipeline Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* spirv/nir: add support for ImageGatherExtendedIlia Mirkin2016-12-161-7/+69
| | | | | | | | | | The strategy is to do the same thing that the GLSL lower_offset_arrays pass does - create 4 separate texture gather ops, one per offset, and read in the results from each gather's w component to recreate the desired result. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* anv: Fix uniform and storage buffer offset alignment limits.Francisco Jerez2016-12-161-2/+2
| | | | | | | | | | | | | | | | | | | | | This fixes a regression in a bunch of image store vulkan CTS tests from commit ad38ba113491869ab0dffed937f7b3dd50e8a735, which started using OWORD block read messages to implement UBO loads. The reason for the failure is that we were giving bogus buffer alignment limits to the application (1B), so the CTS would happily come back with descriptor sets pointing at not even word-aligned uniform buffer addresses. Surprisingly the sampler messages used to fetch pull constants before that commit were able to cope with the non-texel aligned addresses, but the dataport messages used to fetch pull constants after that commit and the ones used to access storage buffers (before and after the same commit) aren't as permissive with unaligned addresses. Cc: <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99097 Reported-by: Mark Janes <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Remove nir_array from lower_locals_to_regsThomas Helland2016-12-161-9/+0
| | | | | | | | We do nothing but initialize it, add to it, and delete it. This is a fallout from removing constant initializer support. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* swr: Implement fence attached work queues for deferred deletion.Bruce Cherniak2016-12-169-54/+255
| | | | | | | Work can now be added to fences and triggered by fence completion. This allows for deferred resource deletion, and other asynchronous tasks. Reviewed-by: George Kyriazis <[email protected]>
* nir: Turn imov/fmov of undef into undefTimothy Arceri2016-12-161-6/+6
| | | | | | | | | | | | | | | Reverting the previous attempt at this a5502a721fd30fd resulted in the following Vulkan test failing. dEQP-VK.glsl.return.return_in_dynamic_loop_dynamic_vertex This time we use the num_components from the alu dest rather than num_inputs to the op to determine the size of the undef. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: "13.0" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99100
* egl/x11: cleanup init codeEric Engestrom2016-12-151-14/+10
| | | | | | | No functional change, just rewriting it in an easier-to-understand way. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* nir/lower_tex: fix number of components in replace_gradient_with_lod()Iago Toral Quiroga2016-12-151-1/+2
| | | | | | | | | | We should make the dest in the textureLod() operation have the same number of components as the destination in the original textureGrad() Fixes regression in ES3-CTS.gtf.GL3Tests.shadow Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99072 Reviewed-by: Kenneth Graunke <[email protected]>
* Revert "nir: Turn imov/fmov of undef into undef."Timothy Arceri2016-12-151-3/+1
| | | | | | | | | | This reverts commit 6aa730000fea84a14b49828a4bb30761d43903bf. This was changing the size of the undef to always be 1 (the number of inputs to imov and fmov) which is wrong, we could be moving a vec4 for example. Acked-by: Kenneth Graunke <[email protected]> Cc: "13.0" <[email protected]>
* i965/vec4: Fix TCS output reads with non-zero component qualifiers.Kenneth Graunke2016-12-141-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | We want to perform the URB read to a vec4 temporary, with no writemask, then issue a MOV to swizzle the data and store it to the actual destination, using the final writemask. We were doing this wrong. For example, let's say we wanted to read a vec2 stored in components 2-3 of a vec4. We would generate a URB read message of: SEND <actual destination>.XY <header with mask set to XY> MOV <actual destination>.XY <actual destination>.ZW This doesn't work, because the URB message reads the .XY components of the vec4, rather than the ZW. It writes to the right place, but with the wrong data. Then the MOV comes along and overwrites it with data that didn't even come from the URB at all. Instead we want to do: SEND <temporary> <header with mask set to ZW> MOV <actual destination>.XY <temporary>.ZW Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/disasm: Decode dataport constant cache control fields.Francisco Jerez2016-12-141-0/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Remove the FS_OPCODE_SET_SIMD4X2_OFFSET virtual opcode.Francisco Jerez2016-12-144-33/+0
| | | | | | Not used anymore. It was just a scalar MOV. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Drop useless access mode override from pull constant generator code.Francisco Jerez2016-12-141-2/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fetch one cacheline of pull constants at a time.Francisco Jerez2016-12-142-19/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Asking the DC for less than one cacheline (4 owords) of data for uniform pull constants is suboptimal because the DC cannot request less than that from L3, resulting in wasted bandwidth and unnecessary message dispatch overhead, and exacerbating the IVB L3 serialization bug. The following table summarizes the overall framerate improvement (with statistical significance of 5% and sample size ~10) from the whole series up to this patch for several benchmarks and hardware generations: | SKL | BDW | HSW SynMark2 OglShMapPcf | 24.63% ±0.45% | 4.01% ±0.70% | 10.31% ±0.38% GfxBench4 gl_manhattan31 | 5.93% ±0.35% | 3.92% ±0.31% | 6.62% ±0.22% GfxBench4 gl_4 | 2.52% ±0.44% | 1.23% ±0.10% | N/A Unigine Valley | 0.83% ±0.17% | 0.23% ±0.05% | 0.74% ±0.45% Note that there are two versions of the Manhattan demo shipped with GfxBench4, one of them is the original gl_manhattan demo which doesn't use UBOs, so this patch will have no effect on it, and another one is the gl_manhattan31 demo based on GL 4.3/GLES 3.1, which this patch benefits as shown above. I haven't observed any statistically significant regressions in the benchmarks I have at hand. Note that the comparatively huge improvement on SKL in the OglShMapPcf test case is due to the combined effect of this patch and the register pressure benefit on SKL+ of "i965/fs: Switch to the constant cache for uniform pull constants.", part of the same series. Going up to 8 oword blocks would improve performance of pull constants even more, but at the cost of some additional bandwidth and register pressure, so it would have to be done on-demand based on the number of constants actually used by the shader. v2: Fix for Gen4 and 5. v3: Non-trivial rebase. Rework to allow the visitor specifiy arbitrary pull constant block sizes. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Expose arbitrary pull constant load sizes to the IR.Francisco Jerez2016-12-144-27/+26
| | | | | | | | | | Change the FS generator to ask the dataport for enough owords worth of constants to fill the execution size of the instruction -- Which means that the visitor now needs to set the execution size correctly for uniform pull constant load instructions, which we were kind of neglecting until now. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Factor out oword block read and write message control calculation.Francisco Jerez2016-12-142-12/+8
| | | | | | | | | We'll need roughly the same logic in other places and it would be annoying to duplicate it. Instead factor it out into a function-like macro that takes the number of dwords per block (which will prove more convenient than taking the same value in owords or some other unit). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Switch to the constant cache for uniform pull constants.Francisco Jerez2016-12-144-91/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts to using the oword block read messages for uniform pull constant loads, as used to be the case until 4c1fdae0a01b3f92ec03b61aac1d3df5. There are two important differences though: Now the L3 cacheability bits are set up correctly for UBOs (since 11f5d8a5d4fbb861ec161f68593e429cbd65d1cd), and we target the constant cache instead of the data cache. The latter used to get no L3 way allocation on boot on all platforms that existed at the time, so oword read messages wouldn't get cached on L3 regardless of the MOCS bits, what probably explains the apparent slowness of oword fetches. Constant cache loads seem to perform better than SIMD4x2 sampler loads in a number of cases, they alleviate some of the cache thrashing caused by the competition with textures for the L1/L2 sampler caches, and they allow fetching up to 128B worth of constants with a single oword fetch message. Note that IVB devices suffer from a hardware bug that leads to serialization of L3 read requests overlapping the same cacheline as result of a (on IVB buggy) mechanism of the L3 to preserve coherency. Since read requests for matching cachelines from any L3 client are not pipelined, throughput may decrease in cases where there are no non-overlapping requests left in the queue that can be processed between them. This situation should be relatively uncommon as long as we make sure that we don't use the 1/2 oword messages in cases where the shader intends to read from any other location of the same cacheline at some other point. This is generally a good idea anyway on all generations because using the 1 and 2 oword messages is expected to waste bandwidth since the minimum L3 request size for the DC is exactly 4 owords (i.e. one cacheline). A future commit will have this effect. I haven't been able to find any real-world example where this would still result in a regression on IVB, but if someone happens to find one it shouldn't be too difficult to add an IVB-specific check to have it fall back to the sampler cache for pull constant loads. Note that on SKL+ this change has the additional benefit of reducing the register footprint of pull constant loads. The following table summarizes the effect of the whole series on several shader-db stats: Total instructions Total cycles BWR: 4571248 -> 4568342 (-0.06%) 123375740 -> 123373296 (-0.00%) ELK: 3989020 -> 3985402 (-0.09%) 98757068 -> 98754058 (-0.00%) ILK: 6383591 -> 6376787 (-0.11%) 143649910 -> 143648914 (-0.00%) SNB: 7528395 -> 7501446 (-0.36%) 103503796 -> 102460370 (-1.01%) IVB: 6949221 -> 6943317 (-0.08%) 60592262 -> 60584422 (-0.01%) HSW: 6409753 -> 6403702 (-0.09%) 60609070 -> 60604414 (-0.01%) BDW: 8043467 -> 7976364 (-0.83%) 68427730 -> 68483042 (0.08%) CHV: 8045019 -> 7977916 (-0.83%) 68297426 -> 68352756 (0.08%) SKL: 8204037 -> 7939086 (-3.23%) 66583900 -> 65624378 (-1.44%) Lost->Gained Total spills Total fills BWR: 5 -> 5 1488 -> 1488 (0.00%) 1957 -> 1957 (0.00%) ELK: 5 -> 5 1489 -> 1489 (0.00%) 1958 -> 1958 (0.00%) ILK: 1 -> 4 1449 -> 1449 (0.00%) 1921 -> 1921 (0.00%) SNB: 0 -> 0 549 -> 549 (0.00%) 52 -> 52 (0.00%) IVB: 13 -> 3 1271 -> 1271 (0.00%) 1162 -> 1162 (0.00%) HSW: 11 -> 0 1271 -> 1271 (0.00%) 1162 -> 1162 (0.00%) BDW: 12 -> 0 1340 -> 1340 (0.00%) 1452 -> 1452 (0.00%) CHV: 12 -> 0 1340 -> 1340 (0.00%) 1452 -> 1452 (0.00%) SKL: 0 -> 120 1269 -> 375 (-70.45%) 1563 -> 690 (-55.85%) v3: Non-trivial rebase. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Let the caller of brw_set_dp_write/read_message control the target cache.Francisco Jerez2016-12-143-42/+43
| | | | | | | | | | | | | | | | | brw_set_dp_read_message already had a target_cache argument, but its interpretation was rather convoluted (on Gen6 the render cache was used if the caller asked for it, otherwise it was ignored using the sampler cache instead), and the constant cache wasn't representable at all. brw_set_dp_write_message used the data cache on Gen7+ except for RENDER_TARGET_WRITE messages, in which case it would use the render cache. On Gen6 the render cache was always used. Instead of the above, provide the shared unit SFID that the caller expects will be used. Makes no functional changes. v3: Non-trivial rebase. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6+: Invalidate constant cache on brw_emit_mi_flush().Francisco Jerez2016-12-141-0/+1
| | | | | | | In order to make sure that the constant cache is coherent with previous rendering when we start using it for pull constant loads. Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Make Gen8 3DSTATE_DS SIMD8 enable work like Gen9+.Kenneth Graunke2016-12-141-1/+4
| | | | | | | This will let us avoid ifdefs. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Rename "DS Function Enable" to "Function Enable".Kenneth Graunke2016-12-142-2/+2
| | | | | | | This makes Gen7/7.5 match Gen8-9. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Reject VkMemoryAllocateInfo::allocationSize == 0Chad Versace2016-12-141-5/+2
| | | | | | The Vulkan 1.0.33 spec says "allocationSize must be greater than 0". Reviewed-by: Nanley Chery <[email protected]>
* egl: Fix crashes in eglCreate*Surface()Chad Versace2016-12-141-2/+2
| | | | | | | | | | | | | Don't dereference a null EGLDisplay. Fixes tests dEQP-EGL.functional.negative_api.create_pbuffer_surface dEQP-EGL.functional.negative_api.create_pixmap_surface Reviewed-by: Mark Janes <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=99038 Cc: "13.0" <[email protected]>
* i965/miptree: Use intel_miptree_copy for mapsJason Ekstrand2016-12-131-12/+8
| | | | | | | | | | What we're really doing is copying a texture not blitting it in the sense of glBlitFramebuffers. Also, the intel_miptree_copy function is capable of properly handling compressed textures which intel_miptree_blit is not. Reviewed-by: Topi Pohjolainen <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97473 Cc: "13.0" <[email protected]>
* i965/blit: Fix the src dimension sanity check in miptree_copyJason Ekstrand2016-12-131-2/+10
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Cc: "13.0" <[email protected]>
* docs: add INTEL_conservative_rasterization to relaese notes for 13.1.0Lionel Landwerlin2016-12-131-0/+1
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* main: add INTEL_conservative_rasterization enum query supportLionel Landwerlin2016-12-132-0/+8
| | | | | | | v2: add extra parameter (Ilia) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* glapi: add missing INTEL_conservative_rasterizationLionel Landwerlin2016-12-131-0/+4
| | | | | | | v2: put enum directly in gl_API.xml (Ilia) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* extensions: update INTEL_conservative_rasterization dependenciesLionel Landwerlin2016-12-131-1/+1
| | | | | | | Suggested by Ilia. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* main: don't error when enabling conservative rasterization on glesLionel Landwerlin2016-12-131-1/+1
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* main: use new driver flag for conservative rasterization stateLionel Landwerlin2016-12-136-7/+19
| | | | | | | | | | | Suggested by Marek. v2: Use new driver flag (Marek) v3: Fix i965 comments (Lionel) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nir/lower_tex: lower gradients on shadow cube maps if lower_txd_shadow is setIago Toral Quiroga2016-12-131-2/+4
| | | | | | | Even if lower_txd_cube_map isn't. Suggested by Ken to make the flag more consistent with its name. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: remove brw_lower_texture_gradientsIago Toral Quiroga2016-12-135-358/+1
| | | | | | | This has been ported to NIR now so we don'tneed to keep the GLSL IR lowering any more. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/nir: enable lowering of texture gradient for shadow samplersIago Toral Quiroga2016-12-131-0/+3
| | | | | | | This gets the lowering on the Vulkan driver too, which is required for hardware that does not have the sample_l_d message (up to IvyBridge). Reviewed-by: Kenneth Graunke <[email protected]>
* nir/lower_tex: add lowering for texture gradient on shadow samplersIago Toral Quiroga2016-12-132-0/+67
| | | | | | | | | | | | | | | | | | | | This is ported from the Intel lowering pass that we use with GLSL IR. This takes care of lowering texture gradients on shadow samplers other than cube maps. Intel hardware requires this for gen < 8. v2 (Ken): - Use the helper function to retrieve ddx/ddy - Swizzle away size components we are not interested in v3: - Get rid of the ddx/ddy helper and use nir_tex_instr_src_index instead (Ken, Eric) v4: - Add a 'continue' statement if the lowering makes progress because it replaces the original texture instruction Reviewed-by: Kenneth Graunke <[email protected]> (v3)
* i965/nir: enable lowering of texture gradient for cube mapsIago Toral Quiroga2016-12-131-0/+1
| | | | | | | | | This gets the lowering on the Vulkan driver too. Fixes Vulkan CTS cube map texture gradient tests in: dEQP-VK.glsl.texture_functions.texturegrad.* Reviewed-by: Kenneth Graunke <[email protected]>
* nir/lower_tex: add lowering for texture gradient on cube mapsIago Toral Quiroga2016-12-132-0/+213
| | | | | | | | | | | | | | | | | | | | | | | | This is ported from the Intel lowering pass that we use with GLSL IR. The NIR pass only handles cube maps, not shadow samplers, which are also lowered for gen < 8 on Intel hardware. We will add support for that in a later patch, at which point we should be able to remove the GLSL IR lowering pass. v2: - added a helper to retrieve ddx/ddy parameters (Ken) - No need to make size.z=1.0, we are only using component x anyway (Iago) v3: - Get rid of the ddx/ddy helper and use nir_tex_instr_src_index instead (Ken, Eric) v4: - When emitting the textureLod operation, copy all texture parameters from the original textureGrad() (except for ddx/ddy) using a loop - Add a 'continue' statement if the lowering makes progress because it replaces the original texture instruction Reviewed-by: Kenneth Graunke <[email protected]> (v3)
* nir/lower_tex: generalize get_texture_size()Iago Toral Quiroga2016-12-131-5/+10
| | | | | | | This was written specifically for RECT samplers. Make it more generic so we can call this from the gradient lowerings too. Reviewed-by: Kenneth Graunke <[email protected]>
* treewide: s/comparitor/comparator/Ilia Mirkin2016-12-1231-85/+85
| | | | | | | | | | git grep -l comparitor | xargs sed -i 's/comparitor/comparator/g' Just happened to notice this in a patch that was sent and included one of the tokens in question. Signed-off-by: Ilia Mirkin <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* nir: Only float and double types can be matricesIan Romanick2016-12-122-19/+24
| | | | | | | | | | | | | | In 19a541f (nir: Get rid of nir_constant_data) a number of places that operated on nir_constant::values were mechanically converted to operate on the whole array without regard for the base type. Only GLSL_TYPE_FLOAT and GLSL_TYPE_DOUBLE can be matrices, so only those types can have data in the non-0 array element. See also b870394. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: Iago Toral Quiroga <[email protected]>
* swr: [rasterizer core/memory] StoreTile: AVX512 progressTim Rowley2016-12-122-222/+138
| | | | | | Fixes to 128-bit formats. Reviwed-by: Bruce Cherniak <[email protected]>
* nir: Move fsat outside of fmin/fmax if second arg is 0 to 1.Matt Turner2016-12-122-0/+25
| | | | | | | | | | instructions in affected programs: 550 -> 544 (-1.09%) helped: 6 cycles in affected programs: 6952 -> 6850 (-1.47%) helped: 6 Reviewed-by: Jason Ekstrand <[email protected]>
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