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* compiler: glsl: silence valgrind warning on write cacheLionel Landwerlin2018-03-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I don't think it actually fixes anything, but that's nice not to have valgrind warnings. It manifests itself when running the piglit test : glsl-fs-raytrace-bug27060 ==2058== Uninitialised byte(s) found during client check request ==2058== at 0xC5BB040: blob_write_bytes (blob.c:152) ==2058== by 0xC595359: write_variable (nir_serialize.c:144) ==2058== by 0xC59560C: write_var_list (nir_serialize.c:192) ==2058== by 0xC5982E4: nir_serialize (nir_serialize.c:1124) ==2058== by 0xC0B729D: brw_program_serialize_nir (brw_program.c:835) ==2058== by 0xC0AB2D6: brw_link_shader (brw_link.cpp:358) ==2058== by 0xC32FE3F: _mesa_glsl_link_shader (ir_to_mesa.cpp:3169) ==2058== by 0xC36C7ED: create_new_program(gl_context*, state_key*) (ff_fragment_shader.cpp:1127) ==2058== by 0xC36C8A6: _mesa_get_fixed_func_fragment_program (ff_fragment_shader.cpp:1157) ==2058== by 0xC1B50AF: update_program (state.c:134) ==2058== by 0xC1B56DF: _mesa_update_state_locked (state.c:352) ==2058== by 0xC1B579A: _mesa_update_state (state.c:386) ==2058== Address 0xf1eab8a is 58 bytes inside a block of size 96 alloc'd ==2058== at 0x4C2CB8F: malloc (vg_replace_malloc.c:299) ==2058== by 0xC0FD306: ralloc_size (ralloc.c:121) ==2058== by 0xC0FD5B1: ralloc_array_size (ralloc.c:208) ==2058== by 0xC452B3B: (anonymous namespace)::nir_visitor::visit(ir_variable*) (glsl_to_nir.cpp:448) ==2058== by 0xC45CE8B: ir_variable::accept(ir_visitor*) (ir.h:428) ==2058== by 0xC46D0B5: visit_exec_list(exec_list*, ir_visitor*) (ir.cpp:1898) ==2058== by 0xC451D2F: glsl_to_nir (glsl_to_nir.cpp:162) ==2058== by 0xC0B5223: brw_create_nir (brw_program.c:79) ==2058== by 0xC0AAB67: brw_link_shader (brw_link.cpp:257) ==2058== by 0xC32FE3F: _mesa_glsl_link_shader (ir_to_mesa.cpp:3169) ==2058== by 0xC36C7ED: create_new_program(gl_context*, state_key*) (ff_fragment_shader.cpp:1127) ==2058== by 0xC36C8A6: _mesa_get_fixed_func_fragment_program (ff_fragment_shader.cpp:1157) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* meson/configure: detect endian.h instead of trying to guess when it's availableEric Engestrom2018-03-235-2/+7
| | | | | | | | | | | Cc: Maxin B. John <[email protected]> Cc: Khem Raj <[email protected]> Cc: Rob Herring <[email protected]> Suggested-by: Jon Turney <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Cc: <[email protected]>
* wayland-drm: do not distribute generated sourcesJuan A. Suarez Romero2018-03-233-13/+36
| | | | | | | | | Instead we will re-generate them again on building. v2: get rid of BUILT_SOURCES (Daniel, Emil) v3: keep BUILT_SOURCES for egl/Makefile.am (Emil) Reviewed-by: Emil Velikov <[email protected]>
* radv: enable TC-compat HTILE for 16-bit depth surfaces on GFX8Samuel Pitoiset2018-03-232-18/+24
| | | | | | | | | | | | | | | | | | | | | The hardware only supports 32-bit depth surfaces, but we can enable TC-compat HTILE for 16-bit depth surfaces if no Z planes are compressed. The main benefit is to reduce the number of depth decompression passes. Also, we don't need to implement DB->CB copies which is fine. This improves Serious Sam 2017 by +4%. Talos and F12017 are also affected but I don't see a performance difference. This also improves the shadowmapping Vulkan demo by 10-15% (FPS is now similar to AMDVLK). No CTS regressions on Polaris10. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_calc_decompress_on_z_planes() helperSamuel Pitoiset2018-03-231-14/+37
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_image_is_tc_compat_htile() helperSamuel Pitoiset2018-03-231-11/+45
| | | | | | | Instead of that huge conditional that's going to be crazy. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir: Rename image intrinsics to image_varJason Ekstrand2018-03-2315-164/+164
| | | | | | | | | | | Generated with git grep -l nir_intrinsic_image | xargs \ sed -i 's/nir_intrinsic_image/nir_intrinsic_image_var/g' and some manual fixing in nir_intrinsics.h Reviewed-by: Timothy Arceri <[email protected]>
* virgl: add ARB_cull_distance support.Dave Airlie2018-03-234-5/+13
| | | | | | | This just allows the properties through to the host if we have cull dist support. Signed-off-by: Dave Airlie <[email protected]>
* broadcom/vc5: Account for InstanceID/VertexID in VPM segment size.Eric Anholt2018-03-221-4/+9
| | | | | Fixes failure in GTF-GLES3.gtf.GL3Tests.draw_instanced.draw_instanced_attrib_size
* broadcom/vc5: Allow FBOs with mixed color formats.Eric Anholt2018-03-221-1/+1
| | | | | This is required by GLES3, fixing GTF-GLES3.gtf.GL3Tests.framebuffer_srgb.framebuffer_srgb_draw
* broadcom/vc5: Add missing support for 2101010_REV vertex attributes.Eric Anholt2018-03-221-0/+8
| | | | | | | Fixes GTF-GLES3.gtf.GL3Tests.vertex_type_2_10_10_10_rev.vertex_type_2_10_10_10_rev_invalid2, where we hadn't thrown a GL error as needed in the extension-disabled case. We want to be exposing the extension anyway.
* broadcom/vc5: Set up a vertex position if the shader doesn't.Eric Anholt2018-03-221-0/+22
| | | | | | Our backend needs some sort of vertex position value to emit the scaled viewport values and such. Fixes potential segfaults in KHR-GLES3.copy_tex_image_conversions.required.cubemap_negx_cubemap_negx
* i965: add performance query support on CNLLionel Landwerlin2018-03-224-1/+10415
| | | | | | | v2: Add brw_oa_cnl.xml to EXTRA_DIST (Emil) Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: perf: add support for new equation operatorsLionel Landwerlin2018-03-221-0/+15
| | | | | | | | Some equations of the CNL metrics started to use operators we haven't defined yet, just add those. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: perf: query topologyLionel Landwerlin2018-03-222-71/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the introduction of asymmetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam to tell userspace what subslices are available. We introduce a new uAPI in the kernel driver to report exactly what part of the GPU are fused and require this to be available on Gen10+. Prior generations can continue to rely on GETPARAM on older kernels. This patch is quite a lot of code because we have to support lots of different kernel versions, ranging from not providing any information (for Haswell on 4.13 through 4.17), to being able to query through GETPARAM (for gen8/9 on 4.13 through 4.17), to finally requiring 4.17 for Gen10+. This change stores topology information in a unified way on brw_context.topology from the various kernel APIs. And then generates the appropriate values for the equations from that unified topology. v2: Move slice/subslice masks fields to gen_device_info (Rafael) v3: Add a gen_device_info_subslice_available() helper (Lionel) Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: devinfo: add helper functions to fill fusing masks valuesLionel Landwerlin2018-03-222-1/+140
| | | | | | | | | | | | | | | | | | | | | | There are a couple of ways we can get the fusing information from the kernel : - Through DRM_I915_GETPARAM with the SLICE_MASK/SUBSLICE_MASK parameters - Through the new DRM_IOCTL_I915_QUERY by requesting the DRM_I915_QUERY_TOPOLOGY_INFO The second method is more accurate and also gives us the EUs fusing masks. It's also a requirement for CNL as this platform has asymetric subslices and the first method SUBSLICE_MASK value is assumed uniform across slices. v2: Change gen_device_info_update_from_masks() to generate topology and call into gen_device_info_update_from_topology (Lionel/Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: devinfo: meson: include drm uapiLionel Landwerlin2018-03-221-1/+1
| | | | | | | Already available with the autotools build. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* drm-uapi: bump headersLionel Landwerlin2018-03-224-36/+189
| | | | | | | Required updates from drm-next for changes in i965. Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]
* intel: devinfo: store slice/subslice/eu masksLionel Landwerlin2018-03-222-1/+91
| | | | | | | | | | | We want to store values coming from the kernel but as a first step, we can generate mask values out the numbers already stored in the gen_device_info masks. v2: Add a helper to set EU masks (Lionel/Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: devinfo: store number of EUs per subsliceLionel Landwerlin2018-03-222-2/+38
| | | | | | | | | | | This will be reused to store values reported by the kernel. The main use case will be for use as the input values of the metric sets equations for the INTEL_performance_queries extension. By storing this information in the gen_device_info we make this non GL specific so this can be reused by Vulkan if we ever have an equivalent extension. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* Revert "meson: merge C and C++ compiler arguments check"Dylan Baker2018-03-221-6/+11
| | | | | | | | | | This reverts commit cb2ddcefa5196fdfeff76f405175c7a6c110eae4. This causes clang to error out building C++ code. The plan is to fix the build to work with clang, but in the mean time we'll just revert this Signed-off-by: Dylan Baker <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* i965/perf: fix config registration when uploading to kernelLionel Landwerlin2018-03-221-1/+1
| | | | | | | | | | | | | | When registring configurations to the kernel for the first time, we run into an issue where the id number is not properly set (we're using the wrong variable). As a result when trying to use that id later on, we get an error. This issue manifest itself the first time you use frameretrace after reboot, subsequent runs are fine. Fixes: 27ee83eaf7e9 ("i965: perf: add support for userspace configurations") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* gallium/winsys/kms: Add support for multi-planesLepton Wu2018-03-221-40/+112
| | | | | | | | | | | | | | | | | | | | | | | Add a new struct kms_sw_plane which delegate a plane and use it in place of sw_displaytarget. Multiple planes share same underlying kms_sw_displaytarget. v2: - add more check for plane size (Tomasz) v3: - split from larger patch (Emil) v4: - no change from v3 v5: - remove mapped field (Tomasz) v6: - remove change-id in commit message (Tomasz) v7: - add revision history in commit message (Emil) Reviewed-by: Tomasz Figa <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Lepton Wu <[email protected]>
* gallium/winsys/kms: Fix possible leak in map/unmap.Lepton Wu2018-03-221-7/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If user calls map twice for kms_sw_displaytarget, the first mapped buffer could get leaked. Instead of calling mmap every time, just reuse previous mapping. Since user could map same displaytarget with different flags, we have to keep two different pointers, one for rw mapping and one for ro mapping. Also introduce reference count for mapped buffer so we can unmap them at right time. v2: - avoid duplicated mapping and leaked mapping (Tomasz) v3: - split from larger patch (Emil) v4: - remove munmap from dt_destory (Emil) v5: - introduce reference count for mapping (Tomasz) - add back munmap in dt_destory v6: - remove change-id in commit message (Tomasz) v7: - remove munmap from dt_destory again (Emil) - add revision history in commit message (Emil) Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Tomasz Figa <[email protected]> Signed-off-by: Lepton Wu <[email protected]>
* broadcom/vc4: add path to nir_builder.hJuan A. Suarez Romero2018-03-221-1/+1
| | | | | | | | As the other VC4 files do. Otherwise, it won't find nir_builder.h v2: add path in source code rather changing autotools (Emil) Reviewed-by: Emil Velikov <[email protected]>
* autotools: add tegra header filesJuan A. Suarez Romero2018-03-222-0/+2
| | | | Reviewed-by: Emil Velikov <[email protected]>
* swr/rast: autotools: add events_private.proto in dist tarball.Juan A. Suarez Romero2018-03-221-0/+1
| | | | Reviewed-by: Emil Velikov <[email protected]>
* radv: autotools: add radv_extensions.h in the generated VULKAN listJuan A. Suarez Romero2018-03-221-1/+2
| | | | Reviewed-by: Emil Velikov <[email protected]>
* anv/radv: autotools: include vulkan_*.h headersJuan A. Suarez Romero2018-03-222-0/+8
| | | | Reviewed-by: Emil Velikov <[email protected]>
* nir: autotools, meson: add GLSL.ext.AMD.h in the files listJuan A. Suarez Romero2018-03-222-0/+2
| | | | Reviewed-by: Emil Velikov <[email protected]>
* intel/compiler: Readd ICL to test_eu_validate.cppMatt Turner2018-03-221-0/+1
| | | | Now that the PCI IDs are upstream, this can be readded.
* intel/compiler: Skip 64-bit type tests when types not availableMatt Turner2018-03-221-0/+19
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Add a Ice Lake PCI IDsAnuj Phogat2018-03-221-0/+8
| | | | Reviewed-by: Rafael Antognolli <[email protected]>
* intel: Disable fast color clear on iclAnuj Phogat2018-03-221-0/+5
| | | | | | | | | Disabling fast color clear makes fbo-clearmipmap test render correct texture in base miplevel. Fast color clear is anyways disabled for non-base miplevels. Acked-by: Matt Turner <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* intel/compiler/icl: Clear "null render target" bit in extended message ↵Jason Ekstrand2018-03-222-0/+6
| | | | | | | | | descriptor Otherwise all our render target writes go no where. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler/icl: Update the assert in brw_stage_has_packed_dispatch()Anuj Phogat2018-03-221-1/+1
| | | | | | | | Rafael ran piglit with the test code enabled and saw no additional GPU hangs. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/common/icl: Disable hiz surface samplingAnuj Phogat2018-03-221-0/+1
| | | | | | | | On gen11+ AUX_HIZ is not a supported value for surfaces being sampled by the 3D sampler. Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/common/icl: Add L3 configAnuj Phogat2018-03-221-0/+18
| | | | | | ICL uses the same L3 configs as CNL, just leaving the SLM configs out. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/tools/aubinator: Drop platform list from print_help()Matt Turner2018-03-221-1/+1
| | | | | | | | We all know the platform names, and I don't want to update this list continually. Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* egl/wayland: Make swrast display_sync the correct queueDerek Foreman2018-03-221-1/+1
| | | | | | | | | | | | | | commit 03dd9a88b0be17ff0ce91e92f6902a9a85ba584a introduced per surface queues, but the display_sync for swrast_commit_backbuffer remained on the old queue. This is likely to break when dispatching the correct queue at the top of function (which can't dispatch the sync callback we're waiting for). The easiest known reproduction case is running weston-subsurfaces under weston --use-pixman Signed-off-by: Derek Foreman <[email protected]> Reviewed-by: Daniel Stone <[email protected]>
* radv: remove unused radv_pipeline::needs_data_cache variableSamuel Pitoiset2018-03-221-1/+0
| | | | Signed-off-by: Samuel Pitoiset <[email protected]>
* meson: merge C and C++ compiler arguments checkEric Engestrom2018-03-221-11/+6
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* omx: always define ENABLE_ST_OMX_{BELLAGIO,TIZONIA}Mathias Fröhlich2018-03-222-2/+11
| | | | | | | | | | | | | | | | | We're trying to be -Wundef clean so that we can turn it on (and eventually make it an error). Note that the OMX code already used `#if ENABLE_ST_OMX_BELLAGIO` instead of #ifdef; I could've changed these, but the point of -Wundef is to catch typos, so we might as well make the change the right way. Fixes: 83d4a5d5aea5a8a05be2 "st/omx/tizonia: Add H.264 decoder" Fixes: b2f2236dc565dd1460f0 "st/omx/tizonia: Add H.264 encoder" Fixes: c62cf1f165919bc74296 "st/omx/tizonia/h264d: Add EGLImage support" Cc: Gurkirpal Singh <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* meson: simplify omx logicMathias Fröhlich2018-03-221-16/+14
| | | | | | | | and let's make sure `with_gallium_omx` is never 'auto' and can only be one of [bellagio, tizonia, disabled]. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* vbo: Remove now duplicate _DrawVAO notification.Mathias Fröhlich2018-03-221-5/+0
| | | | | | | | | | | The DriverFlags.NewArray bit is already set to NewDriverState in _mesa_set_draw_vao since we have actually just above changed the VAOs content. So this can be removed. The _vbo_update_inputs is called by the vbo...recalculate_inputs being set through the same mechanism as described above. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* vbo: Remove now duplicate _vbo_update_inputs from dlist draw.Mathias Fröhlich2018-03-221-3/+0
| | | | | | | | | | | At the current state, _vbo_update_inputs is called from the draw callback if vbo...recalculate_inputs is set. But that is now set of the _DrawVAO or its content or the vertex program mode is changed. So remove _vbo_update_inputs from the direct dlist draw path. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* vbo: Remove redundant set of DriverFlags.NewArray in vbo_bind_arrays.Mathias Fröhlich2018-03-221-1/+0
| | | | | | | | | Now that setting vbo...recalculate_inputs also sets the DriverFlags.NewArray bits into the NewDriverState setting that from vbo_bind_arrays is redundant. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* vbo: Remove vbo...recalculate_inputs from vbo_exec_invalidate_state.Mathias Fröhlich2018-03-221-8/+0
| | | | | | | | This flag is now set when the actual Array._DrawVAO changes. So setting this flag is redundant here. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: A change of gl_vertex_processing_mode needs an array update.Mathias Fröhlich2018-03-221-3/+17
| | | | | | | | | Since arrays also handle the mapping of current values into the disabled array slots, we need to tell the array update code that this mapping has changed. Also mark only dirty if it has changed. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Set DriverFlags.NewArray together with vbo...recalculate_inputs.Mathias Fröhlich2018-03-223-3/+32
| | | | | | | | | | Both mean something very similar and are set at the same time now. For that vbo module to be set from core mesa, implement a public vbo module method to set that flag. In the longer term the flag should vanish in favor of a driver flag of the appropriate driver. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
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