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* tgsi: refactor tgsi_opcode_infer_dst_type()Chia-I Wu2013-05-081-25/+35
| | | | | | | | | | | | | Move the body of tgsi_opcode_infer_dst_type() to a new helper function, tgsi_opcode_infer_type(), and call the helper function from tgsi_opcode_infer_dst_type(). The diff looks complicated simply because the code is moved around. A following commit will make tgsi_opcode_infer_src_type() call tgsi_opcode_infer_type(). Signed-off-by: Chia-I Wu <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* tgsi: reorder opcodes in opcode type inferenceChia-I Wu2013-05-081-24/+24
| | | | | | | | | Reorder opcodes by their assigned numbers. This makes it easier to see the differences between tgsi_opcode_infer_src_type() and tgsi_opcode_infer_dst_type(). Signed-off-by: Chia-I Wu <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* tgsi: clean up exec_tex()Chia-I Wu2013-05-081-168/+52
| | | | | | | | | | | | Make use of tgsi_util_get_texture_coord_dim() to replace the big switch table. There is a subtle difference with this change. When TXP is used with an array texture, the layer is now also projected. This behavior matches the TGSI doc. Since GLSL does not allow TXP on an array texture, I am not sure which behavior is correct or preferred. Signed-off-by: Chia-I Wu <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* tgsi: add tgsi_util_get_texture_coord_dim()Chia-I Wu2013-05-082-0/+94
| | | | | | | | | | | | This util function returns the dimension of the texture coordinates for a texture target, and the location of the shadow reference value. For example, when the texture target is TGSI_TEXTURE_SHADOW2D, the dimension of the texture coordinates is 2, and the location of the ref value is 2 (that is, the Z channel). Signed-off-by: Chia-I Wu <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* nv50: initialize kick_notify callback in nv50_createBryan Cain2013-05-071-0/+1
| | | | | | Fixes infinite loop on startup in Portal and Left 4 Dead 2. NOTE: This is a candidate for the 9.0 and 9.1 branches.
* i965: Use Y-tiled blits to untile for cached mappings of miptrees.Eric Anholt2013-05-071-1/+2
| | | | | | | | Fixes a regression in firefox's unaccelerated compositing path for WebGL with the introduction of Y tiling. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64213 Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add support for Y-tiled blits on gen6+.Eric Anholt2013-05-072-3/+42
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Count occlusion query samples for CopyPixels using the 2D engine.Eric Anholt2013-05-071-0/+3
| | | | | | | | | | We accidentally "fixed" the piglit test for this when introducing Y tiling, since this path stopped being executed. In reenabling this path for Y tiling, we ended up regressing it again, so just fix it. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59439 Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* egl/wayland: Implement EGL_EXT_swap_buffers_with_damageRobert Bragg2013-05-071-3/+26
| | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* egl: Add extension infrastructure for EGL_EXT_swap_buffers_with_damageRobert Bragg2013-05-074-0/+41
| | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* egl: Update to revision 21254 of eglext.hRobert Bragg2013-05-071-3/+42
| | | | | | | This pulls in EGL_EXT_swap_buffers_with_damage. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* gallium: more tgsi documentation updatesRoland Scheidegger2013-05-071-131/+250
| | | | | | | | | Adds the remaining integer opcodes, and some opcodes are moved to more appropriate places, along with getting rid of the (already nearly empty) ps_2_x section. Though the CAP bits for some of these are still a bit in the air so the documentation isn't quite as watertight as is desirable. Reviewed-by: Jose Fonseca <[email protected]>
* ilo: Add missing break statement in aos_tex TGSI_OPCODE_TEX2 case.Vinson Lee2013-05-071-0/+1
| | | | | | | Fixes "Missing break in switch" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* r600g/sb: optimize some cases for CNDxx instructionsVadim Girlin2013-05-072-5/+81
| | | | | | | | | | | | | | We can replace CNDxx with MOV (and possibly eliminate after propagation) in following cases: If src1 is equal to src2 in CNDxx instruction then the result doesn't depend on condition and we can replace the instruction with "MOV dst, src1". If src0 is const then we can evaluate the condition at compile time and also replace it with MOV. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix memory leaksVadim Girlin2013-05-072-1/+7
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix kcache handling on r6xxVadim Girlin2013-05-071-1/+5
| | | | | | | | | Use the same limit for kcache constants in alu group on r6xx as on other chips (two const pairs). Relaxing this will require additional checks to make sure that all 4 consts in the group come from 2 kcache sets (clause limit), probably without noticeable improvements of shader performance. Signed-off-by: Vadim Girlin <[email protected]>
* intel: Remove renderbuffer delete setup from texture wrapping.Eric Anholt2013-05-061-1/+0
| | | | | | This is already set by intel_new_renderbuffer(). Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Make Mesa core set up wrapped texture renderbuffer state.Eric Anholt2013-05-065-34/+7
| | | | | | | | | | Everyone was doing effectively the same thing, except for some funky code reuse in Intel, and swrast mistakenly recomputing _BaseFormat instead of using the texture's _BaseFormat. swrast's sRGB handling is left in place, though it should be done by using _mesa_get_render_format() at render time instead (as-is, it will miss updates to GL_FRAMEBUFFER_SRGB). Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Simplify renderbuffer-for-texture width setup.Eric Anholt2013-05-061-11/+2
| | | | | | | | We're looking for the logical width of our level, which is what image->Width2/Height2 is. The previous code relied on MSAA textures being only level 0. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Make core Mesa allocate the texture renderbuffer wrapper.Eric Anholt2013-05-068-101/+56
| | | | | | Every driver did the same thing. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use brw_blorp_blit_miptrees() for CopyTexSubImage().Eric Anholt2013-05-063-77/+41
| | | | | | | Now that depth resolves are handled there, we don't need to make the temporary renderbuffer. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move blorp resolve setup into brw_blorp_blit_miptrees().Eric Anholt2013-05-062-18/+5
| | | | | | | | | There was some comment about trying to avoid marking resolves in updownsample, but if the downsample is never actually rendered to, then the required resolve tracked in the downsample will never be executed, so who cares? Reviewed-by: Kenneth Graunke <[email protected]>
* gallivm: Fix build for LLVM < 3.3Tom Stellard2013-05-061-0/+6
| | | | | The C API versions of the LLVM multithreaded functions were added in LLVM 3.3.
* r600g/llvm: Parse config values in register / value pairsTom Stellard2013-05-062-4/+31
| | | | Rather than relying on a predetermined order for the config values.
* r600g/llvm: Don't feed LLVM output through r600_bytecode_build()Tom Stellard2013-05-064-395/+21
| | | | | The LLVM backend emits raw ISA now, so we can just its output unmodified.
* r600g/llvm: Don't emit CALL_FS for vertex shadersTom Stellard2013-05-062-8/+10
| | | | The LLVM backend takes care of this now.
* i965: Lower bitfieldInsert.Matt Turner2013-05-061-0/+4
| | | | | | | | | | | | v2: Only lower bitfieldInsert to BFM+BFI (and don't lower bitfieldExtract at all) since three-source instructions are now usable in the vertex shader. v3: Lower bitfield_insert in the same pass with everything else, since it doesn't produce any instructions to be lowered (the other two lowering passes that were in a previous iteration of this series emitted subtractions which needed to be lowered). Reviewed-by: Chris Forbes <[email protected]> [v2]
* i965/vs: Add support for bit instructions.Matt Turner2013-05-064-1/+106
| | | | | | | | | | | v2: Rebase on LRP addition. Use fix_3src_operand() when emitting BFE and BFI2. Add BFE and BFI2 to is_3src_inst check in brw_vec4_copy_propagation.cpp. Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Add support for bit instructions.Matt Turner2013-05-065-0/+142
| | | | | | | | | | | | Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <[email protected]> [v2]
* i965: Add support for emitting and disassembling bit instructions.Matt Turner2013-05-064-0/+28
| | | | | | | | | | | | Specifically bfe - for bitfieldExtract() bfi1 and bfi2 - for bitfieldInsert() bfrev - for bitfieldReverse() cbit - for bitCount() fbh - for findMSB() fbl - for findLSB() Reviewed-by: Chris Forbes <[email protected]>
* i965: Print the correct dst and shared-src types for 3-src instructions.Matt Turner2013-05-061-4/+22
| | | | Reviewed-by: Chris Forbes <[email protected]>
* i965/gen7: Set src/dst types for 3-src instructions.Matt Turner2013-05-061-4/+36
| | | | | | | | | | | | Also update asserts to allow BFE and BFI2, which take (unsigned) doubleword arguments. v2: Allow BRW_REGISTER_TYPE_UD for src1 and src2 as well. Assert that src2.type (instead of src0.type) matches dest.type since it's the primary argument and src0 and src1 might correctly have different types. Reviewed-by: Chris Forbes <[email protected]> [v1]
* i965: Add 3-src destination and shared-source type macros.Matt Turner2013-05-061-0/+11
| | | | Reviewed-by: Chris Forbes <[email protected]>
* i965: Add Gen7+ fields to brw_instruction and add comments.Matt Turner2013-05-061-12/+19
| | | | Reviewed-by: Chris Forbes <[email protected]>
* glsl: Add a pass to lower bitfield-insert into bfm+bfi.Matt Turner2013-05-067-0/+76
| | | | | | | | | | i965/Gen7+ and Radeon/Evergreen+ have bfm/bfi instructions to implement bitfieldInsert() from ARB_gpu_shader5. v2: Add ir_binop_bfm and ir_triop_bfi to st_glsl_to_tgsi.cpp. Remove spurious temporary assignment and dereference. Reviewed-by: Chris Forbes <[email protected]>
* glsl: Add constant evaluation of bit built-ins.Matt Turner2013-05-061-1/+125
| | | | | | | | v2: Order bits from LSB end (31 - count) for ir_unop_find_msb. v3: Add ir_triop_bitfield_extract as an exception to the op[0]->type == op[1]->type assertion in ir_constant_expression.cpp. Reviewed-by: Chris Forbes <[email protected]> [v2]
* glsl: Add support for new bit built-ins in ARB_gpu_shader5.Matt Turner2013-05-066-5/+71
| | | | | | v2: Move use of ir_binop_bfm and ir_triop_bfi to a later patch. Reviewed-by: Chris Forbes <[email protected]>
* glsl: Add new bit built-ins IR and prototypes from ARB_gpu_shader5.Matt Turner2013-05-067-0/+342
| | | | Reviewed-by: Chris Forbes <[email protected]>
* glsl: Rework ir_reader to handle expressions with four operands.Matt Turner2013-05-061-4/+6
| | | | | | | Needed to support the bitfieldInsert() built-in added by ARB_gpu_shader5. Reviewed-by: Chris Forbes <[email protected]>
* mesa: Add infrastructure for ARB_gpu_shader5.Matt Turner2013-05-067-0/+10
| | | | Reviewed-by: Chris Forbes <[email protected]>
* radeon/llvm: Always build libradeonllvm as staticTom Stellard2013-05-063-17/+10
| | | | | | | | | This library is very small, so there is not much to gain from building it as a shared library. Also, when linking statically with LLVM, a shared libradeonllvm exports LLVM symbols and creates problems when used with other shared objects that also link statically to LLVM. Reviewed-by: [email protected]
* radeon/llvm: Use LLVM C API for compiling LLVM IR to ISA v2Tom Stellard2013-05-065-203/+173
| | | | | | | | | | | The LLVM C API is considered stable and should never change, so it is much more desirable to use than the LLVM C++ API, which is constantly in flux. v2: - Split target initialization and lookup into separate functions Reviewed-by: [email protected]
* gallivm: Move LLVMStartMultithreaded() static initializer into gallivmTom Stellard2013-05-062-14/+15
| | | | | | | This does not solve all of the problems with using LLVM in a multithreaded enivronment, but it should help in some cases. Reviewed-by: [email protected]
* radeon/llvm: Don't use the global context when parsing LLVM IRTom Stellard2013-05-061-2/+3
| | | | | | | This leads to crashes when multiple threads try to compile compute shaders in the same time. Fixes a crash in bfgminer when using more than one thread.
* i965: Remove GL_ARB_color_buffer_float from GL core contexts.Eric Anholt2013-05-061-1/+2
| | | | | | | | | Of the 3 controls in the extension, one was kept in GL core and the other two were explicitly deprecated and the reasonable default behavior was encoded in the spec. By not exposing the extension, we avoid shader recompiles when switching between float and unorm color buffers. Reviewed-by: Kenneth Graunke <[email protected]>
* r600g/llvm: Update radeon family mappings for LLVM backendTom Stellard2013-05-062-4/+8
| | | | | New processors were added to the backend to distinguish between GPUs with and without vertex caches.
* android: libsync is needed on Android 4.2+ for any driverChia-I Wu2013-05-061-5/+3
| | | | | | | | Add libsync not only for MESA_BUILD_CLASSIC, but also for MESA_BUILD_GALLIUM. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* android: add ilo to the build systemChia-I Wu2013-05-066-2/+95
| | | | | | | | | It can be selected with BOARD_GPU_DRIVERS := ilo Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* glsl: Flip around "if" statements with empty "then" blocks.Eric Anholt2013-05-051-1/+26
| | | | | | | | | | | | This cleans up some funny-looking code in some unigine shaders I was looking at. Also slightly helps on planeshift and a few shaders in an upcoming Valve release. total instructions in shared programs: 1653715 -> 1653587 (-0.01%) instructions in affected programs: 16550 -> 16422 (-0.77%) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* ilo: correctly set return types of sampler messagesChia-I Wu2013-05-052-0/+3
| | | | | Correctly set the types of the temporaries. We do not want type conversions when moving the results to the final destinations.
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