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* etnaviv: add basic infrastructure for hw queriesChristian Gmeiner2017-10-206-0/+292
| | | | | | | | | | No hardware query is supported yet. v1 -> v2 - removed query_type from strcut etna_hw_sample_provider Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]>
* etnaviv: update headers from rnndbChristian Gmeiner2017-10-205-89/+622
| | | | | | | Update to etna_viv commit 6c9c706. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]>
* relnotes/17.3: EGL_IMG_context_priority is now implementedChris Wilson2017-10-201-0/+1
| | | | | | Suggested-by: Emil Velikov <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Report supported context priorities to EGL/DRIChris Wilson2017-10-201-0/+13
| | | | | | | | | | | | | | | Hook up the RendererQuery for __DRI2_RENDERER_HAS_CONTEXT_PRIORITY to report the available DRM_I915_GEM_CONTEXT_SETPARAM options based on the per-client default context. The kernel will validate the request to change the property, so we get an accurate reflection of available support (based on kernel version and privilege) and we should only have to do it once during screen setup -- although the SETPARAM should be fast, they are still an ioctl each. Signed-off-by: Chris Wilson <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Pass the EGL/DRI context priority through to the kernelChris Wilson2017-10-203-0/+46
| | | | | | | | | | | | | Decode the EGL/DRI priority enum into the [-1023, 1023] range as interpreted by the kernel and call DRM_I915_GEM_CONTEXT_SETPARAM to adjust the priority. We use 0 as the default medium priority (also the kernel default) and so only need adjust up or down. By only doing the adjustment if not setting to medium, we can faithfully report any error whilst setting without worrying about kernel version. Signed-off-by: Chris Wilson <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Record the presence of the kernel schedulerChris Wilson2017-10-201-0/+11
| | | | | | | | | | | Mention to the debug log if the kernel scheduler is enabled; and in particular if it has preemption enabled. Signed-off-by: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Ben Widawsky <[email protected]> Reviewed-by: Joonas Lahtinen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Sync i915_drm.h from kernel for IMG_context_priorityChris Wilson2017-10-201-3/+24
| | | | | | | | | | | | | | | | | | | | | | | Pulling in changes up to kernel commit ac14fbd460d0ec16e7750e40dcd8199b0ff83d0a Author: Chris Wilson <[email protected]> Date: Tue Oct 3 21:34:53 2017 +0100 drm/i915/scheduler: Support user-defined priorities and including the fixup from kernel commit 822a4b673284672af697ccd66e8795f8a712a90d Author: Joonas Lahtinen <[email protected]> Date: Fri Oct 6 13:45:59 2017 +0300 drm/i915: Don't use BIT() in UAPI section for implementing IMG_context_priority. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* egl,dri: Propagate context priority hint to driver->CreateContextChris Wilson2017-10-2016-30/+77
| | | | | | | | | | | | | | | | | | | | Jump through the layers of abstraction between egl and dri in order to feed the context priority attribute through to the backend. This requires us to read the value from the base _egl_context, convert it to a DRI attribute, parse it again in the generic context creator before passing it to the driver as a function parameter. In order to not require us to pass back the actual value of the context priority after creation, we impose that drivers should report the available set of priorities during screen setup (and then they may chose to fail if given an invalid value as that should have been checked at the user boundary.) Signed-off-by: Chris Wilson <[email protected]> Acked-by: Ben Widawsky <[email protected]> # i915/i965 Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* egl: Support IMG_context_priorityChris Wilson2017-10-206-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IMG_context_priority https://www.khronos.org/registry/egl/extensions/IMG/EGL_IMG_context_priority.txt "This extension allows an EGLContext to be created with a priority hint. It is possible that an implementation will not honour the hint, especially if there are constraints on the number of high priority contexts available in the system, or system policy limits access to high priority contexts to appropriate system privilege level. A query is provided to find the real priority level assigned to the context after creation." The extension adds a new eglCreateContext attribute for choosing a priority hint. This stub parses the attribute and copies into the base struct _egl_context, and hooks up the query similarly. Since the attribute is purely a hint, I have no qualms about the lack of implementation before reporting back the value the user gave! v2: Remember to set the default ContextPriority value to medium. v3: Use the driRendererQuery interface to probe the backend for supported priority values and use those to mask the EGL interface. v4: Treat the priority attrib as a hint and gracefully mask any requests not supported by the driver, the EGLContext will remain at medium priority. Signed-off-by: Chris Wilson <[email protected]> Cc: Rob Clark <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radv: don't flush the VS when srcStageMask == TOP_OF_PIPE_BITFredrik Höglund2017-10-201-2/+1
| | | | | | | | | | | | The Vulkan specification says: "... an execution dependency with only VK_PIPELINE_STAGE_TOP_OF_- PIPE_BIT in the source stage mask will effectively not wait for any prior commands to complete." Signed-off-by: Fredrik Höglund <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: mark total_count as MAYBE_UNUSED in CmdSet{Viewport,Scissor}Samuel Pitoiset2017-10-201-2/+2
| | | | | | Fixes two compilation warnings in release build. Trivial. Signed-off-by: Samuel Pitoiset <[email protected]>
* radv: rename radv_cmd_buffer_flush_state() to radv_draw()Samuel Pitoiset2017-10-201-59/+51
| | | | | | | Similar to the dispatch codepath. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: emit primitive restart from radv_emit_draw_registers()Samuel Pitoiset2017-10-201-29/+30
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_emit_draw_registers()Samuel Pitoiset2017-10-201-12/+34
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: refactor indirect draws (+count buffer) with radv_draw_infoSamuel Pitoiset2017-10-201-103/+48
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: refactor indirect draws with radv_draw_infoSamuel Pitoiset2017-10-201-75/+133
| | | | | | | | Indirect draws with a count buffer will be refactored in a separate patch. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: refactor simple and indexed draws with radv_draw_infoSamuel Pitoiset2017-10-201-68/+118
| | | | | | | | | Similar to the dispatch compute logic but for draw calls. For convenience, indirect draws will be converted in a separate patch. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: re-emit VGT_INDEX_TYPE because non-indexed draws overwrite itSamuel Pitoiset2017-10-201-2/+11
| | | | | | | | | Only on CIK and later. We should only update VGT_INDEX_TYPE but it seems easier to re-emit all the index buffer packets. Fixes: 966d66f28f (radv: do not re-emit the index buffer for every draw call) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: clear the dirty flags in the corresponding emit helpersSamuel Pitoiset2017-10-201-2/+8
| | | | | | | This will allow us to fix the VGT_INDEX_TYPE issue properly. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: rename RADV_CMD_DIRTY_RENDER_TARGETS to RADV_CMD_DIRTY_FRAMEBUFFERSamuel Pitoiset2017-10-202-3/+3
| | | | | | | To be consistent with the emit function name. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: move DB_COUNT_CONTROL initialization to si_emit_config()Samuel Pitoiset2017-10-202-1/+5
| | | | | | | CLEAR_STATE will initialize DB_COUNT_CONTROL to 0 for CIK+. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965/vec4: remove setting default LOD in the backendSamuel Iglesias Gonsálvez2017-10-202-21/+0
| | | | | | | It is already done in NIR. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965/fs: remove setting default LOD in the backendSamuel Iglesias Gonsálvez2017-10-201-9/+0
| | | | | | | It is already done in NIR. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* nir: set default lod to texture opcodes that needed it but don't provide itSamuel Iglesias Gonsálvez2017-10-201-0/+13
| | | | | | | | | | | | v2: - Use helper to add a new source to the texture instruction. v3: - Use nir_tex_instr_src_index() to simplify the patch (Jason). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radv: enable GS on GFX9Bas Nieuwenhuizen2017-10-201-3/+1
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: calculate and emit GFX9 GS registers to pipeline state.Bas Nieuwenhuizen2017-10-204-7/+158
| | | | Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: Fix up GS input vgprs.Bas Nieuwenhuizen2017-10-201-0/+15
| | | | Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: Add loading from LDS for merged GS.Bas Nieuwenhuizen2017-10-201-15/+21
| | | | Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: Add ES output to LDS for GFX9.Bas Nieuwenhuizen2017-10-201-8/+49
| | | | Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: Add merged GS function.Bas Nieuwenhuizen2017-10-201-17/+63
| | | | | | [airlied: merged fixup + and fixed up a couple more bits]. Reviewed-by: Dave Airlie <[email protected]>
* radv: Only emit TES when it exists.Bas Nieuwenhuizen2017-10-201-4/+6
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Use control shader presence for detecting tess.Bas Nieuwenhuizen2017-10-201-1/+1
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: fixup tess eval shader when combined.Dave Airlie2017-10-202-6/+23
| | | | | | | | | | This fixes some access to the tess eval shader when it's combined with geometry on gfx9. This is a review of Bas's commit: radv: Prevent crashing by accessing TES for VGT reuse depth. Signed-off-by: Dave Airlie <[email protected]>
* radv: Set VGT_GS_MODE properly for gfx9Bas Nieuwenhuizen2017-10-201-4/+7
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: ensure correct outinfo is picked.Dave Airlie2017-10-201-13/+14
| | | | | | | | | | | | | This struct used to rely on being in a union, it isn't anymore, so we have to pick the correct outinfo struct now. This should fix a regression since the union became a struct. dEQP-VK.tessellation.geometry_interaction.point_size.vertex_set_geometry_set Fixes: 6078a3bd51 (ac/nir: Allow ac_shader_variant_info to contain info about multiple stages.) Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* swr: Rework scratch space allocationGeorge Kyriazis2017-10-192-30/+23
| | | | | | | | | | | | | | | | | Remove allocation of > 2kbyte buffers into context memory in swr_copy_to_scatch_space() (which is used to copy small vertex/index buffers and shader constants to a scratch space to be used by the upcoming draw.) Large shader constant allocations need to be done in the circular scratch buffer instead of context memory, because their values persist across render calls. Also lower SCRATCH_SINGLE_ALLOCATION_LIMIT to 8k, since allocations of larger buffers will get too large for the circular scratch space. Fixes render issues with CEI Ensight. Reviewed-by: Bruce Cherniak <[email protected]>
* radv: Enable tessellation shaders for GFX9.Bas Nieuwenhuizen2017-10-201-1/+1
| | | | | | It mostly works now. Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: init full exec mask for merged shaders.Dave Airlie2017-10-203-0/+12
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: drop unused r600_htile_info.Dave Airlie2017-10-201-9/+0
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix CLEAR_STATE packet length.Dave Airlie2017-10-191-1/+1
| | | | | | | | | | Looking at shader traces I noticed some registers were missing, one of them was being eaten by the wrong clear state length. Fixes: 4f42ea4dc (radv: use CLEAR_STATE for initializing some registers) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* meson: don't build gallium dri target if gallium is disabledDylan Baker2017-10-191-1/+1
| | | | | | | | | | | | Otherwise -Dgallium-drivers= will cause libmesa_gallium to be built and the megadriver install script to attempt to install drivers without any actual drivers being built. fixes: 66f97f6640f5316b36177fd1053f0027eb6ec6cc ("meson: build radeonsi") Reported-by: Rafael Antognolli <[email protected]> Signed-off-by: Dylan Baker <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
* radv: copy indirect lowering settings from radeonsiTimothy Arceri2017-10-201-1/+26
| | | | | | | | | | | | | | It looks the original indirect mask was probably copied from ANV. Sascha Willems demo results: tessellation ~4000 -> ~4200 fps V2: continue lowering local indirects due to llvm deficiencies. Tested-by: Alex Smith <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: stop redundant setting of active_stagesTimothy Arceri2017-10-201-2/+0
| | | | | | We already set it when above in the nir compilation loop. Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: move some code out of loop in store_tcs_output()Timothy Arceri2017-10-201-5/+5
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Modify rsrc1/rsrc2 generation for merged tess.Bas Nieuwenhuizen2017-10-191-7/+16
| | | | | | | No OC_LDS_EN for HS, and the included LS vgpr_comp_cnt is at a different offset. Reviewed-by: Dave Airlie <[email protected]>
* radv: Set correct registers for merged shader rings.Bas Nieuwenhuizen2017-10-191-12/+24
| | | | | | We need different regs to end up in s0/s1. Reviewed-by: Dave Airlie <[email protected]>
* radv: Add GFX9 HS emitting code.Bas Nieuwenhuizen2017-10-191-5/+16
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Remove remaining hard coded references to VS.Bas Nieuwenhuizen2017-10-193-7/+28
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Update GFX9 user data regs for GS/tess.Bas Nieuwenhuizen2017-10-194-14/+25
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Add code to compile merged shaders.Bas Nieuwenhuizen2017-10-194-13/+39
| | | | Reviewed-by: Dave Airlie <[email protected]>
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